Statistical Methods For Agricultural Workers

Cuckoo search (CS) was introduced by Xin-She Yang and Suash Deb in 2009, and it has attracted great attention due to its promising efficiency in solving many optimization problems and real-world applications. In the last few years, many papers have been published regarding cuckoo search, and the relevant literature has expanded significantly. This chapter summarizes briefly the majority of the literature about cuckoo search in peer-reviewed journals and conferences found so far. These references can be systematically classified into appropriate categories, which can be used as a basis for further research.

Cuckoo Search: A Brief Literature Review

Provided is a video coding method and a video decoding method increasing the resolution and quality of images while suppressing an amount of data required for increasing the resolution. A video coding apparatus includes a first orthogonal transformation unit performing discrete cosine transform on an input picture signal, a low-pass filter performing low-pass filtering on the input picture signal, a downsampling unit downsampling the resolution of a low-frequency image signal, a coding unit compressing and coding a reduced image signal, a local decoding unit decoding a coded bit stream, a second orthogonal transformation unit performing discrete cosine transform on a decoded image signal, and a modification information generation unit generating, based on input image DCT coefficients and decoded image DCT coefficients, coefficient modification information used for modifying orthogonal transformation coefficients obtained by performing orthogonal transformation on a decoded video signal obtained from a coded bit stream.

Video encoding method and video decoding method

Cuckoo Search (CS) algorithm is nature inspired global optimization algorithm based on the brood parasitic behavior of cuckoos. It has proved to be an efficient algorithm as it has been successfully applied to solve a large number of problems of different areas. CS employs Levy flights to generate step size and to search the solution space effectively. The local search is carried out using switch probability in which certain percentages of solutions are removed. Though CS is an effective algorithm, still its performance can be improved by incorporating the exploration and exploitation during the search process. In this work, three modified versions of CS are proposed to improve the properties of exploration and exploitation. All these versions employ Cauchy operator to generate the step size instead of Levy flights to efficiently explore the search space. Moreover, two new concepts, division of population and division of generations, are also introduced in CS so as to balance the exploration and exploitation. The proposed versions of CS are tested on 24 standard benchmark problems with different dimension sizes and varying population sizes and the effect of probability switch has been studied. Apart from this, the best of the proposed versions is also tested on CEC 2015 benchmark suite. The modified algorithms have been statistically tested in comparison to the state-of-the-art algorithms, namely grey wolf optimization (GWO), differential evolution (DE), firefly algorithm (FA), flower pollination algorithm (FPA) and bat algorithm (BA). The numerical and statistical results prove the superiority of the proposed versions with respect to other popular algorithms available in the literature.

New cuckoo search algorithms with enhanced exploration and exploitation properties

In digital video image encoding and decoding, a filter type is selected based on symmetrical properties of the images and coefficient values of an interpolation filter are calculated based on the selected filter type. Coefficient values, filter tap-length and selected filter-type are provided in the encoded video data. Coefficient values are also calculated based on a prediction signal representative of the different between a video frame and a reference image. The prediction signal is calculated from the reference image based on a predefined base filter and motion estimation performed on the video frame. The predefined base filter has fixed coefficient values. Coefficient values are selected from interpolation of pixel values in a selected image segment in the video frame. Symmetry properties of images can be a vertical symmetry, a horizontal symmetry and a combination thereof, so that only a portion of the filter coefficients are coded.

Adaptive interpolation filters for video coding

Estimation of jitter in early design cycle of an SoC is necessary to avoid jitter budget conflicts in the design. In this paper, an analysis of power supply induced jitter in a commonly used voltage mode driver architecture in serial links is discussed. The circuit used for the analysis is designed in 28nm FD-SOI technology but the analysis is technology independent. Jitter induced by noise in power delivery networks is analyzed by a transfer function from power supply to the output by a small signal equivalent model. The analysis can be extended generically for System-On-Chip (SoC) level design considerations.

An analysis of power supply induced jitter for a voltage mode driver in high speed serial links

With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical domain methods are based on fitting techniques while the frequency domain methods are based on frequency spectrum analysis. This work describes both statistical domain methods and frequency domain methods. Further, their strengths and limitations are discussed. The algorithms are implemented in MATLAB and the results are extensively verified with Agilent ADS.

A comparative analysis of jitter estimation techniques

An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach.

Fast Analysis of Time Interval Error in Current-Mode Drivers

Integrated System Level Simulations of high speed serial links are necessary for the channel reliability and robustness. Increasing data rates and sharp transition time require high bandwidth systems. System level simulation are required to optimize channel design keeping cost of implementation at moderate or low level while meeting system level channel Bit Error Rate requirement for high bandwidth systems. The parameters which influence the channel and it's interconnect environment are primarily governed by signal integrity and power integrity requirements. In this paper, System Level Robustness Analysis of High Speed Serial Links is demonstrated with external environment considerations taken into account. A strong correlation between measured and simulated results is shown. A generic methodology for high speed serial links is presented with complete analysis of package, board, termination, Signal Quality inrush Droop/Drop (SQiDD), decoupling network etc. I. INTRODUCTION In Semiconductor industry due to tool limitations package analysis, board analysis, mixed signal simulations are performed separately. The complete channel performance is cumulative effect of whole interconnect environment consisting of transceiver, bond wire, package substrate, board, media/cable and termination environment. 'On-the- Board System' means die, package and board integrated together, to form a complete system. There is always a trade off between the various entities which form part of channel environment. In high speed transceivers, Signal Integrity (SI) and Power Integrity (PI) are the most important factors for the designers to keep in the mind while designing a system, as it affects the reliability of transmission at high data rates. This paper presents a Generic Flow for complete On-the- Board System Level Simulation to simulate and analyze the Reliability and Robustness of any PHY ( with example of USB 2.0 PHY), in context of high speed data transmission. Three advantages of SI and PI Analysis are: 1) This analysis is useful to perceive the behavior of whole system at simulation level accurately. 2) This can be used to ensure the Robustness and Reliability of a channel for the targeted bit error rate. 3) It will help the designers to modify the system before it is fabricated. Thus it will reduce product cost and minimize silicon iterations. II. SIGNAL AND POWER INTEGRITY AT SYSTEM LEVEL Signal Integrity means to preserve the signal as it propagates through the media between the transmitter and the receiver (i.e. without distortion in its amplitude shape and jitter performance). At higher speeds, board traces and package signal nets behave like transmission lines. In Serial Links (at system level), there are many types of losses/reflections that may cause distortion in signal quality e.g. reflection loss, insertion loss, coupling etc. Power Integrity (PI) deals with the power delivery network from a voltage source to active devices (ICs) through boards and packages. The noise in the power distribution network mainly affects the system jitter performance as jitter originates from the varying propagation delay caused by shifting bias levels in active circuits. This phenomenon is more prominent with shrinking technologies. Together this environment causes degradation in signal quality which can be primarily measured either by eye diagram or quantitatively by system Bit error rate.

Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links

A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.

Rakesh Malik

Papers

An analysis of power supply induced jitter for a voltage mode driver in high speed serial links

A comparative analysis of jitter estimation techniques

Fast Analysis of Time Interval Error in Current-Mode Drivers

Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links

A minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry