Statistical Methods For Agricultural Workers

Cuckoo search (CS) was introduced by Xin-She Yang and Suash Deb in 2009, and it has attracted great attention due to its promising efficiency in solving many optimization problems and real-world applications. In the last few years, many papers have been published regarding cuckoo search, and the relevant literature has expanded significantly. This chapter summarizes briefly the majority of the literature about cuckoo search in peer-reviewed journals and conferences found so far. These references can be systematically classified into appropriate categories, which can be used as a basis for further research.

Cuckoo Search: A Brief Literature Review

Provided is a video coding method and a video decoding method increasing the resolution and quality of images while suppressing an amount of data required for increasing the resolution. A video coding apparatus includes a first orthogonal transformation unit performing discrete cosine transform on an input picture signal, a low-pass filter performing low-pass filtering on the input picture signal, a downsampling unit downsampling the resolution of a low-frequency image signal, a coding unit compressing and coding a reduced image signal, a local decoding unit decoding a coded bit stream, a second orthogonal transformation unit performing discrete cosine transform on a decoded image signal, and a modification information generation unit generating, based on input image DCT coefficients and decoded image DCT coefficients, coefficient modification information used for modifying orthogonal transformation coefficients obtained by performing orthogonal transformation on a decoded video signal obtained from a coded bit stream.

Video encoding method and video decoding method

Cuckoo Search (CS) algorithm is nature inspired global optimization algorithm based on the brood parasitic behavior of cuckoos. It has proved to be an efficient algorithm as it has been successfully applied to solve a large number of problems of different areas. CS employs Levy flights to generate step size and to search the solution space effectively. The local search is carried out using switch probability in which certain percentages of solutions are removed. Though CS is an effective algorithm, still its performance can be improved by incorporating the exploration and exploitation during the search process. In this work, three modified versions of CS are proposed to improve the properties of exploration and exploitation. All these versions employ Cauchy operator to generate the step size instead of Levy flights to efficiently explore the search space. Moreover, two new concepts, division of population and division of generations, are also introduced in CS so as to balance the exploration and exploitation. The proposed versions of CS are tested on 24 standard benchmark problems with different dimension sizes and varying population sizes and the effect of probability switch has been studied. Apart from this, the best of the proposed versions is also tested on CEC 2015 benchmark suite. The modified algorithms have been statistically tested in comparison to the state-of-the-art algorithms, namely grey wolf optimization (GWO), differential evolution (DE), firefly algorithm (FA), flower pollination algorithm (FPA) and bat algorithm (BA). The numerical and statistical results prove the superiority of the proposed versions with respect to other popular algorithms available in the literature.

New cuckoo search algorithms with enhanced exploration and exploitation properties

In digital video image encoding and decoding, a filter type is selected based on symmetrical properties of the images and coefficient values of an interpolation filter are calculated based on the selected filter type. Coefficient values, filter tap-length and selected filter-type are provided in the encoded video data. Coefficient values are also calculated based on a prediction signal representative of the different between a video frame and a reference image. The prediction signal is calculated from the reference image based on a predefined base filter and motion estimation performed on the video frame. The predefined base filter has fixed coefficient values. Coefficient values are selected from interpolation of pixel values in a selected image segment in the video frame. Symmetry properties of images can be a vertical symmetry, a horizontal symmetry and a combination thereof, so that only a portion of the filter coefficients are coded.

Adaptive interpolation filters for video coding

This paper describes an 11 b ADC realized using a 2.5 b pipelined stage followed by 9 b time interleaved SAR. Presented ADC designed in 65 nm CMOS process occupies 0.3 mm2 area, achieves 59.1 dB SINAD at 100 Ms/s sampling frequency while dissipating 15 mW power from 1.2 V supply and resulting FOM is 0.20 pJ/step.

A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process

An analysis of power supply induced jitter in a high speed serial link is presented in this paper. An equivalent reduced model for serial link is used for the analysis. Jitter induced by the ripples in power delivery network is analyzed by a small signal equivalent model. The effect is modeled by a transfer function which is not technology specific and can be used generically for System-On-Chip (SoC) level design considerations. The analysis is supported by experimental results by simulation in 130nm BiCMoS RF technology and 28nm FDSOI technology (both technologies are of STMicroelectronics).

Analysis of a serial link for power supply induced jitter

A continuous time common mode feedback module is capable of operating in a wide range of input voltages. The common mode feedback module includes a common mode detector and an amplifier for computing and amplifying the difference of a reference voltage and a common mode voltage of a first input signal and a second input signal. The common-mode feedback module includes a common mode resolver and a control voltage generating module coupled to each other to provide a common mode feedback voltage. The common mode feedback module provides a good linearity and a wide bandwidth, without compensation requirements. The common mode feedback module also provides small process corner dependence of bias current and a common mode offset.

Continuous time common-mode feedback module and method with wide swing and good linearity

The presence of harmonic components in a power delivery network affects the performance of the high-speed systems. In this paper, harmonic distortion associated with a 12 V to 1.2 V open-loop buck converter (designed in the BCD 180 nm technology of STMicroelectronics) has been analyzed. The nonlinear behavior of a buck converter has been modeled using Volterra series for expected power supply ripples of 50 Hz. The analysis has been compared with simulation results and shows 5 %, 1 % and 7 % of mean relative error. The difference between the analytical and the simulation results for IP 2h and IP3 h are 2.7 dB and 3 dB, respectively.

Nonlinear modeling and analysis of buck converter using volterra series

This work holds the objective of investigating the performance of conventional Full Adders (FA) at 28nm regime and then proposes a Transmission Gate (TG) based improved FA circuit of reduced Power Delay Product (PDP). In this design the XOR/XNOR nodes have been optimized to operate at submicron level with lower delay. The work provides full voltage swing even at lower operating voltage by avoiding the threshold loss problem. The low leakage feature of TG technology allows it to deliver high energy efficiency. The modified circuit achieves up to 59.14% and 59.36% improvements in worst case delay and PDP respectively as compared to the conventional TG based FA cells for low power mode of operation. Particularly at lower voltage range and higher speed, the performance is considerably fair. Simulations show that the modified FA circuit is efficient in terms of delay as well as extended region of operation. All simulations are performed with Cadence Virtuoso tool and Eldo simulator for 28nm FDSOI technology.

Rakesh Malik

Papers

A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process

Analysis of a serial link for power supply induced jitter

Continuous time common-mode feedback module and method with wide swing and good linearity

Nonlinear modeling and analysis of buck converter using volterra series

An improved low power high speed Full Adder design with 28nm for extended region of operation