Rakshith Saligram

Bio: Rakshith Saligram is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Logic gate & Logic synthesis. The author has an hindex of 7, co-authored 21 publications receiving 183 citations. Previous affiliations of Rakshith Saligram include B.M.S. College of Engineering & University of Southern California.

Design of high speed low power multiplier using Reversible logic: A Vedic mathematical approach

Abstract: Multipliers are vital components of any processor or computing machine. More often than not, performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.

Novel Code Converter Employing Reversible Logic

Abstract: Quantum computing is one of the emerging fields of technology that has been a guiding light for low power VLSI, low power CMOS design, optical information computing, DNAcomputing, Bio-informatics and Nano-technology .A quantum circuit is a model for quantum computation in which a computation is performed by a sequence of quantum gates, which are reversible transformation on a quantum mechanical analog of an n bit register, referred to as an n- qubit. Code converters are required day in and day out. In this paper, a reversible 5421 to binary code converter is implemented.

Optimized reversible vedic multipliers for high speed low power operations

Abstract: Multiplier design is always a challenging task; how many ever novel designs are proposed, the user needs demands much more optimized ones. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. Power dissipation is drastically reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper we aim to enhance the performance of the previous design. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.

Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates

Abstract: Reversible logic is one of the emerging fields of research in the areas of low power computation, Optical information processing, Fault tolerant system, bio information, quantum computation and nanotechnology. ALU is the most vital component of any processing system and need to consume as much less energy as possible in the mean while must be resistant to faults. In this paper the design of a fault tolerant function generator is brought out that can generate up to 16 different Boolean Functions. This unit is the logical unit of an ALU. Refer

A Review on Reversible Logic Gates and their Implementation

Abstract: Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. This paper provides the basic reversible logic gates, which in designing of more complex system having reversible circuits as a primitive component and which can execute more complicated operations using quantum computers. The reversible circuits form the basic building block of quantum computers as all quantum operations are reversible. This paper presents the data relating to the primitive reversible gates which are available in literature and helps researches in designing higher complex computing circuits using reversible gates.

Design of high speed low power multiplier using Reversible logic: A Vedic mathematical approach

Abstract: Multipliers are vital components of any processor or computing machine. More often than not, performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.

Design and synthesis of reversible arithmetic and Logic Unit (ALU)

Abstract: In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU)In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software In the proposed designs, eight arithmetic and four logical operations are performed In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2 Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design

Design and simulation of a reversible ALU by using QCA cells with the aim of improving evaluation parameters

Abstract: One of the most promising solutions for replacing present technologies is Quantum Cellular Automata (QCA) technology Considering its nature, this technology has very low energy losses On the other hand, designing circuits that are without waste of information or reversible can be useful for decreasing energy losses The arithmetic logic unit (ALU) is recognized as the basis of processor systems In this paper, a reversible ALU is proposed along with its implementation and simulation QCA cells that benefit from a new reversible gate that we call NHG (Naghibzadeh---Hoshmand Gate) The proposed NHG gate has better performance in terms of cost and delay when compared with similar gates Thus, the ALU shows acceptable improvement in measures used to evaluate reversible circuits and circuits implemented with QCA cells when compared with previous works

Optimized reversible vedic multipliers for high speed low power operations

Abstract: Multiplier design is always a challenging task; how many ever novel designs are proposed, the user needs demands much more optimized ones. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. Power dissipation is drastically reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper we aim to enhance the performance of the previous design. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.