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Ramchandra M. Kotecha

Bio: Ramchandra M. Kotecha is an academic researcher from National Renewable Energy Laboratory. The author has contributed to research in topics: Power electronics & Gallium nitride. The author has an hindex of 8, co-authored 18 publications receiving 139 citations. Previous affiliations of Ramchandra M. Kotecha include Michigan Technological University & University of Arkansas.

Papers
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Journal ArticleDOI
TL;DR: A fast mission-profile-based simulation strategy for a commercial 1.2-kV all-SiC power module used in a photovoltaic inverter topology using a fast condition-mapping simulation structure and the detailed electro-thermal modeling of the module topology and devices is presented.
Abstract: The reliability analysis and lifetime prediction for SiC-based power modules is crucial in order to fulfill the design specifications for next-generation power converters. This paper presents a fast mission-profile-based simulation strategy for a commercial 1.2-kV all-SiC power module used in a photovoltaic inverter topology. The approach relies on a fast condition-mapping simulation structure and the detailed electro-thermal modeling of the module topology and devices. Both parasitic electrical elements and thermal impedance network are extracted from the finite-element analysis of the module geometry. The use of operating conditions mapping and look-up tables enables the simulation of very long timescales in only a few minutes, preserving at the same time the accuracy of circuit-based simulations. The accumulated damage related to thermo-mechanical stress on the module is determined analytically, and a simple consumed lifetime calculation is performed for two different mission profiles and compared in different operating conditions.

56 citations

Journal ArticleDOI
TL;DR: In this article, a high temperature voltage comparator and an operational amplifier (op-amp) in a 1.2-μm silicon carbide (SiC) CMOS process are described.
Abstract: This paper describes a high temperature voltage comparator and an operational amplifier (op-amp) in a 1.2- $\mu \text{m}$ silicon carbide (SiC) CMOS process. These circuits are used as building blocks for designing a high-temperature SiC low-side over current protection circuit. The over current protection circuit is used in the protection circuitry of a SiC FET gate driver in power converter applications. The op-amp and the comparator have been tested at 400 °C and 550 °C temperature, respectively. The op-amp has an input common-mode range of 0–11.2 V, a dc gain of 60 dB, a unity gain bandwidth of 2.3 MHz, and a phase margin of 48° at 400 °C. The comparator has a rise time and a fall time of 38 and 24 ns, respectively, at 550 °C. The over current protection circuit, implemented with these analog building blocks, is designed to sense a voltage across a sense resistor up to 0.5 V.

40 citations

Journal ArticleDOI
TL;DR: In this article, a unified physics-based insulated-gate bipolar transistor (IGBT) compact model for circuit simulation that predicts the performance of both Si and SiC, n - and p -channel devices is presented.
Abstract: This paper presents a unified physics-based insulated-gate bipolar transistor (IGBT) compact model for circuit simulation that predicts the performance of both Si and SiC, n - and p -channel devices. The model can predict the detailed switching waveforms of these technologies based on its charge-based formulation. Further, this compact IGBT model is presented alongside a unique datasheet-driven parameter extraction process. The parameter extraction process enables users to quickly extract model parameters from data typically published without the need of taking physical measurements. The model has been validated with both Si and SiC devices for static and dynamic characteristics. The SiC IGBTs used for validation are a 12.5-kV n -channel device and a 13-kV p -channel device, while the Si IGBT chosen was IXDH30N120 from IXYS Corp. (Milpitas, CA, USA). This is the only IGBT model that predicts the performance of both n - and p -channel, Si and SiC devices, providing more freedom for the development of complex power electronics circuit designs. The convergence of the model has been verified by implementing a complex circuit consisting of both a dc–dc converter and a dc–ac inverter. The results presented here show that the unified model can be used to describe the behavior of a wide range of Si and SiC IGBT circuits. This paper is accompanied by a Verilog-A source code and a power point file demonstrating the model parameter extraction sequence.

18 citations

Proceedings ArticleDOI
26 Dec 2018
TL;DR: A compact electro-thermal SiC Power MOSFET model implemented in LTSpice is presented in this paper and the dynamic validation has been shown using a double-pulse test circuit.
Abstract: A compact electro-thermal SiC Power MOSFET model implemented in LTSpice is presented in this paper. A 1200 V, 90A CREE SiC power MOSFET (C2M0025120D) has been used in this work to illustrate the parameter extraction and experimental model validation. The dynamic validation has been shown using a double-pulse test circuit. The convergence has been tested with the 4-switch topology of an inverter and a comparison between MAST, Verilog-A and CREE's empirical model of the same device has also been presented.

13 citations


Cited by
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Journal ArticleDOI
TL;DR: The failure mechanisms, lifetime modeling, and reliability-oriented design of three types of SCs in energy storage applications are reviewed.

132 citations

Journal ArticleDOI
01 Aug 2021
TL;DR: In this article, the authors report the monolithic integration of enhancementmode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits.
Abstract: Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters. Through the monolithic integration of enhancement-mode n-type and p-type gallium nitride field-effect transistors, complementary integrated circuits including latch circuits and ring oscillators can be created for use in high-power and high-frequency applications.

97 citations

Journal ArticleDOI
TL;DR: In this paper, the authors provide a comprehensive overview, address existing challenges, and unfold new research opportunities regarding the SiC power converter real-time lifetime prediction and extension, including component-level failure modes and mechanisms.
Abstract: Remaining useful lifetime prediction and extension of Si power devices have been studied extensively. Silicon carbide (SiC) power devices have been developed and commercialized. Specifically, SiC mosfet s have been utilized for the next generation high-voltage, high-power converters with smaller size and higher efficiency, covering various mainstream applications, including photovoltaic systems, electric vehicles, solid-state transformers, and more electric ships and airplanes. However, the SiC-based devices have different failure modes and mechanisms compared with Si counterparts. Therefore, a comprehensive review is critical to develop accurate lifetime prediction and extension strategies for SiC power converter systems. The SiC power device component-level failure modes and mechanisms are first investigated. Different accelerated lifetime tests and component-level lifetime models are then compared. Power converter system-level offline lifetime modeling techniques and software tools are further summarized. Besides, the SiC power converter condition monitoring strategies and health indicators are surveyed. The online measurement challenges are also studied. Furthermore, the system-level lifetime extension strategies are reviewed. By integrating device physics, statistical modeling, reliability engineering, and mechanical engineering with power electronics, this article is intended to provide a comprehensive overview, address existing challenges, and unfold new research opportunities regarding the SiC power converter real-time lifetime prediction and extension.

91 citations

Journal ArticleDOI
TL;DR: In this article, the authors present a thorough review of development of SiC IGBT in the past 30 years and summarize the progresses of models, structure design, and performance in SiC ICIGBT.
Abstract: Along with the increasing maturity for the material and process of the wide bandgap semiconductor silicon carbide (SiC), the insulated gate bipolar transistor (IGBT) representing the top level of power devices could be fabricated by SiC successfully This article presents a thorough review of development of SiC IGBT in the past 30 years The progresses of models, structure design, and performance in SiC IGBT are summarized The challenges resulting from fabrication process and switching characteristics are discussed and analyzed in detail The experimental results and existing problems in SiC IGBT-based applications are summarized in the end

75 citations

Journal ArticleDOI
TL;DR: In this article, the authors present the first experimental demonstrations of large-area Ga2O3 Schottky barrier diodes (SBDs) packaged in the bottom-side-cooling and double-sidecooling configurations, and for the first time, characterizes the surge current capabilities of these packaged SBDs.
Abstract: Ultrawide-bandgap gallium oxide (Ga2O3) devices have recently emerged as promising candidates for power electronics; however, the low thermal conductivity ( k T) of Ga2O3 causes serious concerns about their electrothermal ruggedness. This letter presents the first experimental demonstrations of large-area Ga2O3 Schottky barrier diodes (SBDs) packaged in the bottom-side-cooling and double-side-cooling configurations, and for the first time, characterizes the surge current capabilities of these packaged Ga2O3 SBDs. Contrary to popular belief, Ga2O3 SBDs with proper packaging show high surge current capabilities. The double-side-cooled Ga2O3 SBDs with a 3 × 3-mm2 Schottky contact area can sustain a peak surge current over 60 A, with a ratio between the peak surge current and the rated current superior to that of similarly-rated commercial SiC SBDs. The key enabling mechanisms for this high surge current are the small temperature dependence of on -resistance, which strongly reduces the thermal runaway, and the double-side-cooled packaging, in which the heat is extracted directly from the Schottky junction and does not need to go through the low- k T bulk Ga2O3 chip. These results remove some crucial concerns regarding the electrothermal ruggedness of Ga2O3 power devices and manifest the significance of their die-level thermal management.

52 citations