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Author

Ramendra Singh

Bio: Ramendra Singh is an academic researcher from Indian Institute of Technology Delhi. The author has contributed to research in topics: Silicon on insulator & Semiconductor device modeling. The author has an hindex of 5, co-authored 12 publications receiving 70 citations.

Papers
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Journal ArticleDOI
TL;DR: This letter investigates the RF performance of a negative capacitance FinFET using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices, and finds that NC-FinFET’s cut-off frequency is a function of LaTeX, and observes that the self-heating effect in NC-finFET increases with increase ininline-formula.
Abstract: In this letter, we have investigated the RF performance of a negative capacitance FinFET (NC-FinFET) using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices. This physics-based RF model is then coupled self-consistently with the Landau-Khalatnikov equation to obtain the RF NC-FinFET model. For the first time, we report, here, the impact of ferroelectric thickness ( ${t}_{\textit {fe}}$ ) scaling on RF performance of NC-FinFET and find that NC-FinFET’s cut-off frequency ( ${f}_{\text {T}}$ ) is a function of ${t}_{\textit {fe}}$ . We also observe that the self-heating effect in NC-FinFET increases with increase in ${t}_{\textit {fe}}$ , mainly due to increase in DC current, which can be easily compensated by decreasing supply voltage. Finally, we show that NC-FinFET can achieve similar analog/RF performance as the base FinFET, even at a reduced ${V}_{\mathrm{ DD}}$ .

45 citations

Journal ArticleDOI
TL;DR: In this paper, a 3D quasi-atomistic LER model is used for the analysis of LER-induced mismatch in JL, IM, and AM NWFETs.
Abstract: Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for realization of advanced CMOS technology nodes. Due to small nanowire dimensions, NWFETs are vulnerable to the impact of process-induced random local variations, such as the line edge roughness (LER) and random dopant fluctuation (RDF). NWFETs have three different device modes, namely, the inversion mode (IM), the accumulation mode (AM), and the junctionless (JL) mode. In this paper, a 3-D quasi-atomistic LER model is used for the analysis of LER-induced mismatch in JL, IM, and AM NWFETs. We have also compared the impact of 3-D LER with that of 2-D LER. In addition, another emerging simulation methodology known as statistical impedance field method is utilized to analyze the impact of RDF on the three flavors of NWFETs. We show that JL NWFETs have much higher mismatch due to both LER and RDF than their IM and AM NWFET counterparts with otherwise identical device structure.

39 citations

Journal ArticleDOI
TL;DR: The characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz shows a good correlation with the measurement data and the self-heating effect (SHE) is significant in short-channel silicon on insulator (SOI) NWFets.
Abstract: In this paper, we report the characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz. The self-heating effect (SHE) in NWFETs is investigated experimentally using the small-signal output conductance ( ${g}_{{\text {ds}}}$ ) technique. The frequency-dependent complex thermal impedance, ${Z}_{{\text {th}}}({f})$ , is extracted by fitting an ${n}$ th-order thermal network with the experimental data. We show that the temperature rise $\Delta {T}$ (=85 °C) due to SHE is significant in short-channel silicon on insulator (SOI) NWFETs. Finally, we have evaluated the RF figure of merit (FOM) for these NWFETs as ${f}_{T}$ (=70 GHz) and ${f}_{\text {max}}$ (=80 GHz). We also report the RF performance metric sensitivity on temperature, $\partial {f}_{\text {max}}/\partial {T}_{{\text {amb}}}$ ( $\approx -0.104$ GHz/K). The reported BSIM-CMG compact model shows a good correlation with the measurement data.

11 citations

Journal ArticleDOI
TL;DR: A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented and the proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations.
Abstract: An analytical model of parasitic capacitance in inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness ( ${T}_{\textsf {iox}}$ ) and inserted-oxide recess ( ${T}_{\textsf {rec}}$ ), is shown using the proposed model and TCAD simulations.

9 citations

Proceedings ArticleDOI
01 Dec 2016
TL;DR: In this paper, the authors have performed DC model parameter extraction and statistical process variations for 7nm target device using industry standard BSIM-CMG model using 1000 Monte Carlo simulation runs.
Abstract: In this work, we have performed DC model parameter extraction and statistical process variations for 7nm node target device using industry standard BSIM-CMG model. Nanowire FET is the device architecture of choice for 7nm node due to improved short channel control and high layout density. BSIM-CMG is the surface potential based compact model for common multiple gate devices. Process variations become even worse beyond 14nm node and tend to limit chip performance and yield. In this work process variations have been modeled, starting from long to nominal gate length devices, by performing 1000 Monte Carlo simulation runs. The mean and standard deviation values obtained have been compared with 7nm target values obtained by inputs from various sources. Process variations have been applied and validated over wide range of geometries and bias conditions. Excellent agreement with the target values has been obtained.

8 citations


Cited by
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01 Jan 2013
TL;DR: Aujourd’hui toute l’électronique se concentre sur une puce, and les logiciels de simulation utilisés sont plutôt du type VHDL, voire mixte continu/événementiel, mais dont the plupart sont inspirés de SPICE.
Abstract: SPICE est un logiciel qui m’a beaucoup émerveillé lorsque j’étais étudiant, de par sa puissance et sa simplicité d’utilisation. Il est vrai que nous faisions beaucoup de travaux pratiques en électronique, et le simple fait de pouvoir mettre son circuit sous forme de liste, appelée netlist, et de le simuler était une découverte fascinante. SPICE a servi de modèle à nombre d’autres programmes de simulation, dans les universités et dans l’industrie, grâce à son modèle précoce Open Source. Aujourd’hui toute l’électronique se concentre sur une puce, et les logiciels de simulation utilisés sont plutôt du type VHDL [1], voire mixte continu/événementiel [2], mais dont la plupart sont inspirés de SPICE. Actuellement, on édite de manière graphique son schéma et on lance directement la simulation depuis son interface graphique. Ce qu’il faut savoir c’est que bon nombre de ces interfaces graphiques construisent une netlist et c’est un SPICE adapté qui fera la simulation par-derrière. La première version de SPICE date de 1972 et a été écrite en fortran, rapidement suivie par la deuxième version en 1975. Il faudra attendre 1989 pour voir la troisième version (définitive) de SPICE, écrite en C. Il est remarquable d’observer que la troisième version fût la dernière, avec des mises à jour mineures et qui se déclinent en lettre, la dernière étant 3f5. Aujourd’hui, et dans cet article, on utilisera Ngspice [3] qui est basé sur la dernière version de SPICE, et qui se trouve sous licence GNU GPL2. Il est fourni par le groupe de développement gEDA [4] qui a repris le flambeau pour le développement de tous les logiciels de simulation ou de conception de circuits électroniques.

159 citations

Journal ArticleDOI
TL;DR: In this article, the structural and electronic properties of Ga2O3 (α, β, κ, and ) are compared, and band offsets between the phases and other common wideband-gap semiconductors are determined.
Abstract: Ga2O3 is an ultra-wide-band-gap semiconductor especially promising for power electronic applications. One advantage of this material is its ability to exist in different phases, which may add flexibility to device design, namely through polarization engineering of two-dimensional electron gases. Although much is known about monoclinic β-Ga2O3, much less is known about many basic electronic properties of other phases. In this work, four of the most common phases of Ga2O3 (α, β, κ, and ) are investigated with first-principles calculations based on hybrid density functional theory. The structural and electronic properties of each phase are compared, and band offsets between the phases and other common wide-band-gap semiconductors are determined. All four phases of Ga2O3 are found to exhibit self-trapping holes, large Mg acceptor ionization energies, deep oxygen vacancy donor levels, and low-lying valence-band maxima. In addition, all phases have large valence-band offsets but small or modest conduction-band offsets with GaN, SiC, and Si. With AlN and diamond, all Ga2O3 phases have large conduction-band and valence-band offsets.

31 citations