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Author

Ramune Nagisetty

Other affiliations: University of California, Berkeley
Bio: Ramune Nagisetty is an academic researcher from Intel. The author has contributed to research in topics: PMOS logic & NMOS logic. The author has an hindex of 14, co-authored 27 publications receiving 1412 citations. Previous affiliations of Ramune Nagisetty include University of California, Berkeley.

Papers
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Journal Article•DOI•
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Abstract: A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

728 citations

Proceedings Article•DOI•
13 Dec 2004
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Abstract: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57/spl mu/m/sup 2/. Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

264 citations

Proceedings Article•DOI•
05 Dec 1999
TL;DR: In this paper, the authors report a very high performance 100 nm gate length CMOS transistor structure operating at 1.2-1.5 V and 3 nA/m I/sub OFF.
Abstract: We report a very high performance 100 nm gate length CMOS transistor structure operating at 1.2-1.5 V. These transistors are incorporated in a 180 nm logic technology generation. Various process enhancements are incorporated to significantly improve transistor current drive capability relative to the results published by Yang et al. (1998). Unique transistor features responsible for achieving high performance are described. NMOS and PMOS devices demonstrate drive current of 1.04 mA//spl mu/m and 0.46 mA//spl mu/m respectively at 1.5 V and 3 nA//spl mu/m I/sub OFF/. These are the best drive currents reported to date at fixed I/sub OFF/. They represents 10% drive current improvement for both NMOS and PMOS devices relative to the results published by Yang without any change in gate-oxide thickness. High performance is demonstrated down to 1.2 V. Inverter delay of less than 10 psec is reported at 1.5 V at very moderate I/sub OFF/ values.

71 citations

Proceedings Article•DOI•
05 Dec 2005
TL;DR: In this article, an advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented at 1V and off current of 100nA/mum.
Abstract: An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented At 1V and off current of 100nA/mum, transistors have record currents of 121mA/mum and 071mA/mum for NMOS and PMOS respectively This industry leading 65nm technology is currently in high volume manufacturing

70 citations

Journal Article•DOI•
TL;DR: A systematic study of the reflectance oximeter sensor design in terms of component geometry, light emitter and detector spacing, and the use of an optical barrier between the emitters and detector to maximize sensor performance is reported.
Abstract: Recent progress in printed optoelectronics and their integration in wearable sensors have created new avenues for research in reflectance photoplethysmography (PPG) and oximetry. The reflection-mode sensor, which consists of light emitters and detectors, is a vital component of reflectance oximeters. Here, we report a systematic study of the reflectance oximeter sensor design in terms of component geometry, light emitter and detector spacing, and the use of an optical barrier between the emitter and the detector to maximize sensor performance. Printed red and near-infrared (NIR) organic light-emitting diodes (OLEDs) and organic photodiodes (OPDs) are used to design three sensor geometries: (1) Rectangular geometry, where square OLEDs are placed at each side of the OPD; (2) Bracket geometry, where the OLEDs are shaped as brackets and placed around the square OPD; (3) Circular geometry, where the OLEDs are shaped as block arcs and placed around the circular OPD. Utilizing the bracket geometry, we observe 39.7% and 18.2% improvement in PPG signal magnitude in the red and NIR channels compared to the rectangular geometry, respectively. Using the circular geometry, we observe 48.6% and 9.2% improvements in the red and NIR channels compared to the rectangular geometry. Furthermore, a wearable two-channel PPG sensor is utilized to add redundancy to the measurement. Finally, inverse-variance weighting and template matching algorithms are implemented to improve the detection of heart rate from the multi-channel PPG signals.

53 citations


Cited by
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Journal Article•DOI•
TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Abstract: All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

2,090 citations

Journal Article•DOI•
TL;DR: In this article, the latest advances in valley-tronics have largely been enabled by the isolation of 2D materials (such as graphene and semiconducting transition metal dichalcogenides) that host an easily accessible electronic valley degree of freedom, allowing for dynamic control.
Abstract: Semiconductor technology is currently based on the manipulation of electronic charge; however, electrons have additional degrees of freedom, such as spin and valley, that can be used to encode and process information. Over the past several decades, there has been significant progress in manipulating electron spin for semiconductor spintronic devices, motivated by potential spin-based information processing and storage applications. However, experimental progress towards manipulating the valley degree of freedom for potential valleytronic devices has been limited until very recently. We review the latest advances in valleytronics, which have largely been enabled by the isolation of 2D materials (such as graphene and semiconducting transition metal dichalcogenides) that host an easily accessible electronic valley degree of freedom, allowing for dynamic control. The energy extrema of an electronic band are referred to as valleys. In 2D materials, two distinguishable valleys can be used to encode information and explore other valleytronic applications.

1,799 citations

Journal Article•DOI•
25 Apr 2008-Science
TL;DR: A simple approach to high-performance, stretchable, and foldable integrated circuits that integrate inorganic electronic materials, including aligned arrays of nanoribbons of single crystalline silicon, with ultrathin plastic and elastomeric substrates.
Abstract: We have developed a simple approach to high-performance, stretchable, and foldable integrated circuits. The systems integrate inorganic electronic materials, including aligned arrays of nanoribbons of single crystalline silicon, with ultrathin plastic and elastomeric substrates. The designs combine multilayer neutral mechanical plane layouts and "wavy" structural configurations in silicon complementary logic gates, ring oscillators, and differential amplifiers. We performed three-dimensional analytical and computational modeling of the mechanics and the electronic behaviors of these integrated circuits. Collectively, the results represent routes to devices, such as personal health monitors and other biomedical devices, that require extreme mechanical deformations during installation/use and electronic properties approaching those of conventional systems built on brittle semiconductor wafers.

1,588 citations

Journal Article•DOI•
R. Ho1, Ken Mai1, Mark Horowitz1•
01 Apr 2001
TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
Abstract: Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.

1,486 citations

Journal Article•DOI•
David J. Frank1, R.H. Dennard1, E. J. Nowak1, Paul M. Solomon1, Yuan Taur1, Hon-Sum Philip Wong1 •
01 Mar 2001
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

1,417 citations