Ran-Hong Yan

Bio: Ran-Hong Yan is an academic researcher from Bell Labs. The author has contributed to research in topics: CMOS & Phase-locked loop. The author has an hindex of 4, co-authored 4 publications receiving 697 citations. Previous affiliations of Ran-Hong Yan include Realtek.

Impact of distributed gate resistance on the performance of MOS devices

Abstract: This paper describes the impact of gate resistance on cut-off frequency (f/sub T/), maximum frequency of oscillation (f/sub max/), thermal noise, and time response of wide MOS devices with deep submicron channel lengths. The value of f/sub T/ is proven to be independent of gate resistance even for distributed structures. An exact relation for f/sub max/ is derived and it is shown that, to predict f/sub max/, thermal noise, and time response, the distributed gate resistance can be divided by a factor of 3 and lumped into a single resistor in series with the gate terminal. >

A UWB CMOS transceiver

Abstract: A direct-conversion ultra-wideband (UWB) transceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13-/spl mu/m CMOS technology, the transceiver provides a total gain of 69-73 dB and a noise figure of 6.5-8.4 dB across three bands, and a TX 1-dB compression point of -10 dBm. The circuit consumes 105 mW from a 1.5-V supply.

Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS

Abstract: Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology. Configured as a master-slave circuit, the divider achieves a maximum speed of 13.4 GHz with a power dissipation of 28 mW. The phase-locked loop employs a current-controlled oscillator and a symmetric mixer to operate at 3 GHz with a tracking range of /spl plusmn/320 MHz, an rms jitter of 2.5 ps, and a phase noise of -100 dBc/Hz while dissipating 25 mW. >

A 0.13 /spl mu/m CMOS UWB transceiver

Abstract: A direct-conversion UWB transceiver for mode 1 OFDM applications employs three resonant networks and three PLLs. Designed in a 0.13 /spl mu/m CMOS technology, the transceiver provides a total gain in the range of 69 to 73 dB, an NF in the range of 5.5 to 8.4 dB across three bands, and a TX P/sub 1dB/ of -10 dBm. The circuit consumes 105 mW from a 1.5 V supply.

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Fundamentals of Modern VLSI Devices

Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

A 1.5-V, 1.5-GHz CMOS low noise amplifier

Abstract: A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-/spl mu/m CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices.

A study of phase noise in CMOS oscillators

Abstract: This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-/spl mu/m CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB.

A 1.5 V, 1.5 GHz CMOS low noise amplifier

Abstract: A 1.5 GHz low noise amplifier for a Global Positioning System (GPS) receiver has been implemented in a 0.6 /spl mu/m CMOS process. This amplifier provides a forward gain of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. To the authors' knowledge, this represents the lowest noise figure reported to date for a CMOS amplifier operating above 1 GHz.