Showing papers by "Rao Tummala published in 1991"

Ceramic and Glass‐Ceramic Packaging in the 1990s

Abstract: A broad overview of packaging involving interconnecting, powering, protecting, and cooling semiconductor chips to meet a variety of computer system needs is presented. The general requirements for ceramics in terms of their thermal, mechanical, electrical, and dimensional control requirements are presented, both for high-performance and low-performance applications. Glass-ceramics are identified as the best candidates for high-performance systems, and aluminum nitride, alumina, or mullite are identified for low-performance systems. Glass-ceramic/copper substrate technology is discussed as an example of high-performance ceramic packaging for use in 1990s. Lower-dielectric-constant ceramics such as composites of silica, borosilicate, and cordierite, with or without polymers and porosity, are projected as potential ceramic substrate materials by the year 2000.

Ceramic substrate having a protective coating thereon and a method for protecting a ceramic substrate

Abstract: Disclosed is a ceramic substrate having a protective coating on at least one surface thereof which includes: a ceramic substrate having at least one electrically conductive via extending to a surface of the substrate; an electrically conductive I/O pad electrically connected to at least one of the vias; an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet; and a protective layer of polymeric material fully encapsulating the I/O pad, wherein the layer of polymeric material protects the I/O pad from corrosion. Also disclosed is a method of protecting a ceramic substrate from corrosion, the ceramic substrate of the type having a plurality of electrically conductive vias extending to a surface of the substrate, a multilayer metallic I/O pad electrically connected to at least one of the vias, and an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet, the method comprising the step of: encapsulating fully the I/O pad with a protective layer of polymeric material, wherein the layer of polymeric material protects the I/O pad from corrosion. In a preferred embodiment, the I/O pin is selectively exposed to plasma ashing to remove any errant polymeric material from the pin shank, thereby assuring electrical contact to the pin shank.

Ceramic and Glass-Ceramic Packaging in the 1990s

Abstract: A broad overview of packaging involving interconnecting, powering, protecting, and cooling semiconductor chips to meet a variety of computer system needs is presented. The general requirements for ceramics in terms of their thermal, mechanical, electrical, and dimensional control requirements are presented, both for high-performance and low-performance applications. Glass-ceramics are identified as the best candidates for high-performance systems, and aluminum nitride, alumina, or mullite are identified for low-performance systems. Glass-ceramic/copper substrate technology is discussed as an example of high-performance ceramic packaging for use in 1990s. Lower-dielectric-constant ceramics such as composites of silica, borosilicate, and cordierite, with or without polymers and porosity, are projected as potential ceramic substrate materials by the year 2000.

A ceramic substrate having a protective coating and method of protection

Abstract: Disclosed is a ceramic substrate having a protective coating on at least one surface thereof which includes: a ceramic substrate (52) having at least one electrically conductive via (54) extending to a surface of the substrate; an electrically conductive I/O pad (56) electrically connected to at least one of the vias; an I/O pin (58) brazed to the I/O pad (56), the brazed pin having a braze fillet (60); and a protective layer of polymeric material (62) fully encapsulating the I/O pad, wherein the layer of polymeric material protects the I/O pad, from corrosion. Also disclosed is a method of protecting a ceramic substrate from corrosion, the ceramic substrate of the type having a plurality of electrically conductive vias extending to a surface of the substrate, a multilayer metallic I/O pad electrically connected to at least one of the vias, and an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet, the method comprising the step of: encapsulating fully the I/O pad with a protective layer of polymeric material wherein the layer of polymeric material protects the I/O pad from corrsoion. In a preferred embodiment, the I/O pin is selectively exposed to plasma ashing to remove any errant polymeric material from the pin shank, thereby assuring electrical contact to the pin shank.