Showing papers by "Rao Tummala published in 1998"

Improvements and recent advances in nanocomposite capacitors using a colloidal technique

Abstract: In this work, a colloidal technique is used to improve the dielectric properties of nanocomposite materials and to achieve thin film deposition (<5 /spl mu/m) on large area substrates using meniscus coating. Using this technique, improved particle dispersion is achieved, which in turn allows for higher volume loading (increased dielectric constant), small variation of dielectric constant across the substrate, and thin-film deposition with lower particle-induced defects. Appropriate dispersants and fillers particularly applicable to meniscus coating of these composite materials were found which allowed the coated and cured composite material to attain high relative dielectric constant (typical 40). Non-meniscus-coated samples with dielectric constants as high as 74 were achieved by varying the particle size distribution.

Electroless Ni-P/Ni-W-P thin-film resistors for MCM-L based technologies

Abstract: A novel technique of fabricating MCM-L compatible integrated resistors on large area substrates is presented. Electroless plated Ni-P/Ni-W-P alloys are used to achieve resistivity values in the range of 5-50 ohm/square and absolute temperature coefficient of resistivity below 50 ppm//spl deg/C, which is sufficient to satisfy many resistor application needs. Fine line structures (<50 /spl mu/m linewidth) are achieved by a three step process: electroless plating a thin (100-200 /spl Aring/) seed layer on patterned photoresist; lift-off of regions of the seed layer by dissolution of the photoresist; and electroless plating of the resultant structures in the seed layer to the desired thickness to achieve a specific sheet resistance. Improvements in seeding uniformity of the initial blanket seed layer were achieved by use of an organosilane-based surface treatment prior to deposition, as well as tight control of temperature across the substrate during plating. A test vehicle consisting of various resistor structures to evaluate electrical and mechanical properties, processing conditions, and reliability was designed and fabricated. Electrical properties, (including scattering parameters (S-parameters) of the resistor structures up to 20 GHz), temperature coefficient of resistivity (TCR), and power handling capabilities of the resistor structures on different substrates are presented.

MCM-L Compatible Integrated Resistors And Capacitors

Abstract: Integration of passive components offers inherent benefits such as reduced size, density, cost, and improved packaging efficiency and reliability. An integrated RC network requiring relatively large capacitance and resistance was selected as a model for integration of R and C components using low temperalare PWB compatible fabrication processes. Ohmega-Ply resistor/conductor laminates and photodefinable epoxies filled with high K ceramic powders were used as candidate materials for fabrication of embedded resistors and thin film capacitors. In order to reduce in-plane device area, multilayer (currently, two-layer) capacitors were stacked in the thickness direction. Meniscus coating of filled polymer dielectrics over large area (12 in x 12 in) was evaluated for cost and manufacturability advantages. This paper discusses the design, choice of materials, and fabricatilon issues of an integrated RC device. 1. Introlduction The Packaging Research Center at Georgia Tech is in the process of developing low temperalure MCM-L based processes suitable ICR L

SLIM: third generation of packaging beyond MCM, CSP, flipchip and micro-via board technologies

Abstract: The Packaging Research Center at Georgia Tech proposes to address packaging needs by using a technical vision for the next generation of packaging similar to what ICs did for transistors over the last four decades: continued integration to ever higher transistor density while maintaining manufacturing cost. This technical vision for the next generation of packaging looks at the current industry standard of a QFP wire bonded to the IC on a surface mount board; ceramic discretes are also surface mounted. For applications such as cellular phones, camcorders, or magnetic disk drives, the packaging efficiency, defined as the ratio of the area of all silicon and other ICs to the area of system-level board, is about 7% with this technology. The technical vision of integration of all of these packaging levels into one level with dielectrics, conductors, capacitors, resistors, inductors, and optoelectronics (as waveguides) is proposed to raise this efficiency to about 80%. This is primarily for two reasons: (1) discretes are now embedded into the substrate and thus take up no additional substrate surface area, and (2) all of the integration and extensive thin film wiring allows ICs to be flip-chip bonded "wall-to-wall" on the substrate. This integrated module can be a single chip, chip-scale module in the short-term, referred to as SCIM (single chip integrated module), the size of which is no bigger than the IC itself with as much as 5000 I/Os, or an integrated multichip module referred to as IMCM or single level integrated module board (SLIM).