Showing papers by "Rao Tummala published in 1999"

System on chip or system on package

Abstract: The authors propose a new system design paradigm, the system on package, which uses electronic product reengineering to meet time-to-market and performance requirements. The system on package promises a higher return on investment than the system on chip.

Method for manufacturing a multilayer wiring substrate

Abstract: Generally, the present invention can be viewed as providing a method for manufacturing a multilayer wiring substrate. Briefly described, the method can be broadly conceptualized by the following steps: forming a first conductive connection on a first insulating layer; forming a conductive post on the first conductive connection; forming a second insulating layer on the first conductive connection, the first insulating layer, and the conductive post; exposing the conductive post by removing a portion of the second insulating layer; and forming a second conductive connection on the second insulating layer such that the second conductive connection is electrically connected to the first conductive connection via the conductive post. The second insulating layer can be formed via dry film lamination. In addition, the conductive posts can be exposed by either forming holes in the second insulating layer or by roughening the surface of the second insulating layer.

Do chip size limits exist for DCA

Abstract: Solder joints, the most widely used flip chip on board (FCOB) interconnects, have relatively low structural compliance due to the large thermal expansion mismatch between Si die and organic substrate. The PWB CTE is almost an order of magnitude greater than that of the IC. Under operating and testing conditions, this mismatch subjects solder joints to large creep strains and leads to early solder joint failure. FCOB structure reliability can be enhanced by applying an epoxy-based underfill between chip and substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate to constrain the CTE mismatch locally. However, CTE mismatch effects are assumed to become more severe with increasing chip size. Even with the use of underfill, it is supposed that there are limits on chip size in flip chip applications. Fraunhofer Institute IZM/Technical University are collaborating with Georgia Tech to study fundamental limits of direct chip attach. The objectives are: to understand material and mechanical issues related to thermo-mechanical reliability of direct chip attach; to determine fundamental chip size limits by taking process conditions, process-induced defects, underfill material property requirements, geometry limitations and service environment into consideration; to investigate the impact of geometrical, material and operating parameters on FCOB assembly thermomechanical reliability and to determine an optimum combination of parameters to minimize delamination, solder joint fatigue, chip cracking and/or excessive warpage; to validate FEA simulations experimentally.

The needs, evolution, status and challenges of microelectronics packaging education in the US

Abstract: It is only within the last 10 years that packaging has begun to be viewed as an important discipline. Several universities have started to provide packaging courses as well as special focuses on certificate programs. This paper describes human resource needs in terms of quality and quantity of packaging engineers, the evolution of electronic packaging education at all levels in the US to meet these human resource needs, and discusses how the next generation of microelectronics packaging education should be conducted to meet the needs of US industry.

Development of low viscosity, high dielectric constant (k) polymers for integral passive applications

Abstract: The integration of passive components (resistors, capacitors, inductors) into printed wiring boards (PWBs) has become a very significant part of electronic packaging technology. The biggest advantages of integrating passive components into a substrate are reduced assembly costs, minimized PWB real estates, reduced component dimensions, and improved electrical performance. One of the challenges of incorporating passives into a PWB is choosing a suitable material that satisfies both electrical and reliability needs. This research seeks to develop high dielectric constant (k) materials for integral capacitors and integral decoupling capacitors. More specifically, the goal of this work is to develop low viscosity, high k polymers for use in conjunction with high k ceramic materials, such as lead magnesium niobate, to form high k polymer-ceramic composites. Polymers with viscosity values ranging from 0.13 to 0.15 Pa/spl middot/s were formulated and characterized by differential scanning calorimetry (DSC), dielectric analysis (DEA), and rheology. The polymers were mixed in different volume percentages with lead magnesium niobate-lead titanate (PMN-PT) ceramic powder by ball milling. DSC and DEA were used to characterize this composite material. Several methods for increasing dielectric constant were identified and implemented. Prototype capacitors were fabricated in order to measure k values for the composite materials. Dielectric constant values as high as 62 were achieved with samples containing relatively low volume percentages of PMN-PT ceramic powder.