Showing papers by "Rao Tummala published in 2002"

RF-system-on-package (SOP) for wireless communications

Abstract: Anew industrial revolution, often called the “third wave” or information technology (IT), is in the making. The products of this revolution will require entirely different systems hardware technologies: those with multifunctions, such as digital, analog, RF, and optical circuitries. RF and microwave design and packaging have been established as key technologies of this revolution. The demand for increasingly higher rates of data, voice, and video drives RF technology to ever higher frequencies where bandwidth for channel capacity is easy to find. Such emerging high-performance applications as personal communication networks, wireless local-area networks (WLAN), and RF-optical networks have defined a trend toward more flexible and reconfigurable systems. They impose very stringent specifications never before reached in term of low noise, high linearity, low power consumption, small size and weight, and low cost. The RF front-end module is the foundation of these systems, and its integration poses a great challenge. Microelectronics technology, since the invention of the transistor, has revolutionized many aspects of electronic products. This integration and cost path has led the microelectronics industry to believe that this kind of progress can go on forever, leading to so-called “system-on-chip” (SOC) for all applications. But it is becoming clear that the production of a complete solution for the new wireless communication front-end is still a dream. When you consider the characteristics of an RF front-end module  high performance up to 100-GHz operating frequency  a large number of high-performance discrete passive components  design flexibility

Integrated RF architectures in fully-organic SOP technology

Abstract: Future wireless communications systems require better performance, lower cost, and compact RF front-end footprint. The RF front-end module development and its level of integration are, thus, continuous challenges. In most of the presently used microwave integrated circuit technologies, it is difficult to integrate the passives efficiently with required quality. Another critical obstacle in the design of passive components, which occupy the highest percentage of integrated circuit and circuit board real estate, includes the effort to reduce the module size. These issues can be addressed with multilayer substrate technology. A multilayer organic (MLO)-based process offers the potential as the next generation technology of choice for electronic packaging. It uses a cost effective process, while offering design flexibility and optimized integration due to its multilayer topology. We present the design, model, and measurement data of RF-microwave multilayer transitions and integrated passives implemented in a MLO system on package (SOP) technology. Compact, high Q inductors, and embedded filter designs for wireless module applications are demonstrated for the first time in this technology.

Design of inductors in organic substrates for 1-3 GHz wireless applications

Abstract: High Q inductors with maximum quality factors in the range of 180-60 have been obtained at frequencies in the 1-3 GHz band for inductances in the range of 1 nH to 20 nH using a low-temperature organic laminate build-up process. This is the first time such high Q inductors have been demonstrated in this technology. The different inductor designs, optimization schemes, and trade-offs between different topologies, have been discussed in this paper.

Liquid crystal polymers (LCP) for high performance SOP applications

Abstract: Electronic devices will increasingly rely on new materials with improved properties such as lower coefficient of thermal expansion preferably close to silicon, higher modulus, lower permittivity & loss, lower moisture absorption, better thermal conductivity, good dimensional stability, and more importantly reduced warpage particularly after the build-up process. The thermal properties of LCP's have led to increasing interest for the packaging community. This work deals with the evaluation of LCP's for future electronic packaging applications. LCP samples obtained from industry were analyzed using TA instruments. The samples with the properties best matched to the needs of future electronic packaging applications will be chosen based on the thermal analysis data presented for (i) fabrication of a base substrate using solely reinforced LCP, (ii) evaluating LCP for use as a carrier film, (iii) performing laser ablation techniques for via formation in the build up layers, and (iv) plating of the vias and the films for through hole Z-direction connections and X, Y, signal lines. In the present work, application of LCP as a dielectric layer for the system-on-package process has been evaluated. It is expected that the reinforced LCP films can also be utilized as a substrate material thereby providing the unique opportunity for superior compatibility between the substrate and the dielectric layer.

Reliability assessment of microvias in HDI printed circuit boards

Abstract: Accelerating adoption of CSP and flip-chip area array packaging for high performance and hand-held applications is the main driving force for high-density substrates and printed circuit boards. At the Packaging Research Center, Georgia Institute of Technology (PRC-GT), ultra-fine line high density interconnect (HDI) substrate technology is being developed as part of the system-on-a-package (SOP) research and testbed efforts to meet these emerging requirements. To be adopted by industry, this novel technology must demonstrate the critical elements of high reliability and low cost processing. The HDI and microvias structures discussed in this paper were fabricated on high Tg organic substrates using a sequential build-up process, and were subject to extensive liquid to liquid thermal shock testing. All 75 /spl mu/m microvias and above successfully passed 2000 cycles without failure, and first failure occurred at 1000 cycles for 50 /spl mu/m microvias on a 50 /spl mu/m thick dielectric layer. Microvia down to 25 /spl mu/m diameter on a 25 /spl mu/m thick dielectric layer have passed 2000 cycles with zero failures. Cross-sectioning confirmed that failures were caused by process related defects, such as thin electrolytic copper plating. This paper will discuss the reliability results of the PRC HDI microvias process and methods to improve the mechanical reliability of small photo defined microvias fabricated on similar laminate substrates.

High density packaging in 2010 and beyond

Abstract: As microsystems continue to move towards higher speed and microminiaturization, the demands for interconnection density both on the IC and the package increases tremendously. With the shift towards nano ICs by 2003 with 100 nm features, pitch of area array I/Os of the nano ICs will move towards 20-100 micron. Increasing system functionality and system-on-a-chip will place demands on the package to support extremely high digital clock speeds beyond 5 GHz, RF signals to 40 GHz, and optical data rates beyond 100 Gbps all on a single, highly integrated package or board. A completely new paradigm shift in high density packaging is required to meet these complex requirements. Current trends both in IC and systems packaging including SIP, wafer level packaging are steps in the right direction, but represent partial system solutions. The Packaging Research Center at Georgia Tech has been developing system-on-a-package (SOP) technology to integrate digital, RF, and optical, all on a multi-function, microminiaturized board. This paper reviews systems, IC, and high density packaging trends and summarizes the latest PRC developments in high density SOP packaging technology.

High performance spiral inductors embedded on organic substrates for SOP applications

Abstract: This paper presents the design, measured data, and systematic analysis of spiral embedded inductors fabricated on standard organic substrates using low-cost, large-area MCM-L technology. Several configurations for inductors were investigated to optimize the inductor layout dimensions such as conductor width, number of turns, inner diameter, spacing between inductor and ground, and inductor area. A maximum Q of 100 was measured for a 3.6 nH inductor at 1.8 GHz on an organic substrate with a self resonance frequency of 10.6 GHz within an inductor core area of 0.72 mm/sup 2/. The effects of configurational variables on inductor characteristics such as quality factor, self-resonance frequency, and inductance are discussed. High-Q inductors embedded on organic substrates can find numerous RF and microwave system-on-package (SOP) applications, such as VCOs, IF/RF bandpass filters, LNAs, etc., in which IC chips are flip-chip mounted on the package substrate.

Determination of propagation constants of transmission lines using 1-port TDR measurements

Abstract: The propagation constants of transmission lines were measured from 1-port TDR measurements. Since the TDR measurement is a 1-port measurement, error can be smaller than 2-port measurement techniques. Moreover, the available frequency is determined by the rise time of the TDR step pulse unlike TRL methods. The propagation constant of a lossy transmission line was extracted from DC to 10 GHz. Simulation of the lossy transmission line using the extracted propagation constant shows good agreement with TDR measurement, demonstrating the accuracy of the TDR measurement technique.

Evaluation of liquid crystal polymers for high performance SOP application

Abstract: Electronic devices increasingly rely on new materials with improved properties such as lower coefficient of thermal expansion (preferably close to silicon), higher modulus, lower permittivity and dielectric loss, lower moisture absorption better thermal conductivity, higher dimensional stability, and most importantly reduced warpage particularly after the build-up process. Liquid crystal polymers (LCPs) have led to increasing interest for the packaging community due to their superior thermal and electrical properties. The targeted applications areas for LCPs are RF packaging, due to their low loss and low dielectric constant over a wide frequency range (Fukutake and Inoue, 2002; Fukutake, 1998; Jayaraj et al, 1995; Lawrence, 2000; Jayaraj et al, 1996; Yue et al, 1999,), near hermitic plastic sealing due to superior moisture barrier properties (Jayaraj et al, 1997), flex circuits and microvia laminates for high density interconnection (Corbett et al, 2000; Yue and Chan, 1998). This paper is focused toward possible application of LCP as a dielectric material for lamination on PWB and other engineered organic substrates. Commercially available LCP samples were analyzed using a variety of thermal analysis techniques. Based on thermal properties such as coefficient of thermal expansion (CTE), thermal degradation temperature and modulus, samples were selected for applications as a dielectric material. It is expected that a low CTE dielectric such as LCP will further reduce the dielectric film stress even when the CTE of the chip is matched with that of the substrate.

RF-microwave multi-band design solutions for multilayer organic system on package integrated passives

Abstract: We present multi-band design solutions for integrated passives using multilayer organic (MLO) process technology for RF and microwave System on Package (SOP) module development. The components developed in this technology include embedded high-Q compact inductors and filters designed in three frequency bands: S, C and Ku applicable for Bluetooth, MMDS, IEEE802.11a WLAN and satellite communications. Measured inductor Q-factor as high as 182 and Self-Resonant-Frequency (SRF) as high as 20 GHz, which represents the highest Q in its frequency range reported to date in a multilayer technology, have been demonstrated. A time domain electromagnetic modeling technique is also use to characterize the passive devices.

Digital and RF integration in system-on-a-package (SOP)

Abstract: The Packaging Research Center (PRC) is developing system-on-a-package (SOP) technology, as a complimentary alternative to SOC, as the fundamental building block for next generation convergent systems with computing, telecom and consumer capabilities with data and voice. Any systems of this nature have to provide not only high-speed digital, but also high bandwidth optical, analog, RF and perhaps MEMS functions. The SOP technology being pursued at PRC with embedded digital, optical and RF functions addresses this need, optimizing the IC and the package for functions, performance, cost, size and reliability. The PRC is developing this complimentary alternative to SOC using a three tier strategy consisting of fundamental research innovations, enabling technology developments and system-level testbeds. Individual digital, optical and RF testbeds have been developed to enable the integration of novel packaging technologies like embedded passive and optical components, high density global interconnections and wafer level flip-chip assembly. A phased system testbed is being evolved from these three testbeds to develop new SOP convergent system platforms for a digital/optical/RF system implementation. This paper summarizes the latest PRC accomplishments in the development of SOP baseline processes and system testbeds and updates the progress from basic research and technology integration to system testbeds for SOP.

The role of stiff base substrates in warpage reduction for future high-density-wiring requirements

Abstract: The role of warpage on future high density wiring requirements is investigated. These studies also show the impact of the gap between mask and the substrate arising out of warpage on the width of fine lines when vacuum cannot reduce the effect of warpage. For 100 micron wide lines, substrates with warpage greater then 50 microns are found to result in 30% error in the actual transferred pattern, while warpage greater than 200 microns results in the complete elimination of photoresist openings. The via-pad misalignment for a 300 mm substrate was measured to be 116 microns for FR4 substrate while the value is less than 25 microns for AlN. The % displacement, defined as the distance between the via center and pad center normalized with respect to the pad diameter, is hence more than 25% in case of a warped substrate, while it is found to be less than 10% for stiffer substrates. Hence, as feature size becomes smaller, accurate translation of mask features on to the substrate during photolithography will be limited by the warpage of the substrate and hence stiffer substrates are required to meet next-generation high-density wiring needs.

Design and fabrication of high aspect ratio fine pitch interconnects for wafer level packaging

Abstract: The Packaging Research Center (PRC) at Georgia Tech has been exploring and evaluating novel compliant nano interconnect designs to enable high density I/O architecture for the next generation chip assembly. Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. We propose high aspect ratio interconnects as a solution that can support both electrical and mechanical requirements. The fabrication of these interconnects is similar to the standard IC fabrication and involves only one additional step beyond the standard CMOS wafer processing, thus making it a cost effective wafer level process. Extensive modeling was carried out to design 40 /spl mu/m pitch interconnects with optimized electrical and mechanical properties. The fabrication of fine-pitch copper interconnects with aspect ratio of 1:5 was demonstrated as a low-cost wafer level process. Results show that these interconnects provide the optimal combination of electrical and mechanical requirements and hence provides a viable solution for next-generation electronic packaging that can support extremely high I/O density.

C-band oscillator using high-Q inductors embedded in multi-layer organic packaging

Abstract: We present C-band oscillators with external high-Q inductors: wire-bond inductors and embedded inductors in a Multi-Layer Organic (MLO) board fabricated by a thick-film MCM-L technology. The phase-noise performance of oscillators is compared with the oscillator using on-chip inductors. Inductors are designed to obtain high quality factor in C-band. The phase-noise performance of the oscillator with on-chip inductors measures -108 dBc/Hz at 600 kHz offset frequency, and that of the oscillator with external inductors shows -113 dBc/Hz at the same offset. Using MLO inductors, the phase-noise is better than the oscillator with on-chip inductors and comparable to the oscillator with wire-bond inductors. To our knowledge, this is the first C-band oscillator using inductors embedded in the multi-layer organic packaging technology. This is also the first report comparing the performance of oscillators using three different inductor technologies: on-chip integration, wire-bonding, and multi-layer organic packaging technology.

Novel hydrothermal processing (<100/spl deg/C) of ceramic-polymer composites for integral capacitor applications

Abstract: Synthesis of high K thin films via low cost low temperature process remains a major challenge in realizing integral capacitors for SOP applications. The current study explores synthesis of Barium Titanate by Hydrothermal process. BaTiO/sub 3/ films using hydrothermal synthesis at temperatures less than 100/spl deg/C has been reported previously. However, these films are typically porous and hence give a very low dielectric constant and low yield. Precursor films are hence heat-treated and densified at temperatures higher than 300/spl deg/C to obtain a good yield and hence a high dielectric constant which makes these processes incompatible with organic based build-up processes. Hence the process was modified to infiltrate a polymer into these porous films to improve the yield, reliability and subsequent processing of these films. BaTiO/sub 3/ films were also synthesized on Titanium foils with the goal of integrating them with the standard PWB processes. Dielectric constant of 700 and specific capacitances more than 1000 nF/cm/sup 2/ have been achieved by this modified hydrothermal process. The microstructure of the film and the polymer infiltration can be optimized to synthesize reliable films with high dielectric constant and low loss tangent. Hence, the film morphology and thickness are being studied to optimize the processing conditions for reliable films.

Fabrication of ultra-fine line circuits on PWB substrates

Abstract: One of the greatest challenges facing the packaging industry at present is the availability of organic substrates capable of routing and interconnecting high I/O fine pitch area array flip chip. These substrates require line widths and spacing of 3.5 to 12 /spl mu/m for flip chip systems applications supporting chip I/O densities of 5 K-10 K/cm/sup 2/ and pitch of 50 to 100 /spl mu/m. The system-on-a-package (SOP) module being developed at the Packaging Research Center (PRC) at Georgia Tech is focused on providing lines and spaces in the 6 to 10 /spl mu/m range and microvias in the 10 to 15 /spl mu/m range to support these applications. The PRC has been evaluating low cost materials and processes by integrating them into the SOP substrates. These substrates demonstrate the very fine and ultra fine line widths and spaces necessary to meet next-generation interconnect density requirements. Line widths and spaces of 15 to 25 /spl mu/m and microvia diameters of 50 /spl mu/m on low-cost organic substrates has been demonstrated in the fabrication of SOP testbed prototypes. Processes for 10 /spl mu/m fine lines and spaces coupled with 25 /spl mu/m small microvia interconnect are currently being developed for inclusion in the next phase of PRC SOP prototype test beds. The PRC plans further exploration into developing low-cost processes capable of achieving line widths and spaces of 6 to 10 /spl mu/m for inclusion into future SOP test bed prototypes. A fine line and width structure made of 4 /spl mu/m copper lines on build-up laminate (FR-4) is discussed in this paper. Additionally, we present highlights of a novel stack-via technology that enables the wiring density necessary to meet future interconnect requirements as indicated in the SIA semiconductor roadmap.

Simulation of Eye-Diagrams on Lossy Transmission Lines using Extracted Data from 1-port TDR Measurements

Abstract: The propagation constant and characteristic impedance of transmission lines were measured from 1port TDR measurements. Using the extracted data, eyediagrams of lossy transmission lines were simulated based on a non-physical RLGC model. Conventional W element simulation for the lossy transmission lines were performed in Hspice for comparison with the non-physical RLGC model. The eye-diagram of the non-physical RLGC model showed more loss, as is expected in lossy transmission lines.

Hands-on module packaging education at Georgia Tech

Abstract: The Design Build and Operate (DBO) course at PRC (the Packaging Research Center at Georgia Institute of Technology) provides hands-on experience in SOP (System on a Package) packaging for undergraduate and graduate students. DBO consists of a sequence of two courses: Design Build Operate I (DBO I), which focuses on substrate fabrication and Design Build Operate II (DBO II), which focuses on module assembly. This paper presents an overview of the second component of the sequence, the DBO II (module) course. A detailed presentation of the experiments conducted and their results are presented. A user friendly software which helps students to conduct virtual designs and fabrication processes is also presented.

Development and characterization of embedded thin-film capacitors for mixed signal applications on fully organic system-on-package technology

Abstract: As part of the system on package (SOP) concept being developed at the Packaging Research Center (PRC), Georgia Institute of Technology, a test vehicle to demonstrate the suppression of simultaneous switching noise (SSN) using embedded decoupling capacitors with polymer-ceramic composites as the dielectric was implemented. Similarly, the test vehicle was used for the characterization of the dielectric to demonstrate its feasibility in RF applications. One of the key factors for the integration of future systems is the incorporation of functionality into the substrate by using low cost, low temperature (<150/spl deg/C) sequential build-up processes. In order for embedded decoupling capacitors to be effective in mixed signal systems, the material properties of the dielectric must be well characterized. For the decoupling and RF capacitor, the capacitance and the self-resonant frequency values are critical properties. Also, the impact and importance of varying dielectric thickness on a large area was studied. The capacitors developed and characterized here compare well to some commercially available surface mount components; furthermore, this work represents the first demonstration of a single embedded capacitor technology for both low to mid-frequency decoupling and RF applications on a large area fully organic substrate. This study will have significant impact on high-end mixed signal systems.

Low temperature (<100/spl deg/C) hydrothermal synthesis of high K-low loss BaTiO/sub 3/ films for integral capacitors

Abstract: Integration of passive components like resistors, inductors and capacitors into the substrate offers a number of advantages including better electrical performance, miniaturization, reliability and reduced part counts. The integral capacitor requirements in today's systems vary widely from 1-20 pF for signal capacitors in RF applications to 0.01- 0.1 /spl mu/F for digital, RF and power decoupling. Ferroelectric thin films can provide this wide range of properties but their integration has been rendered impossible due to either high temperatures involved in processing or high cost associated with thin film deposition techniques. In this paper we report synthesis of low loss hydrothermal BaTiO/sub 3/ thin films via a low temperature process - hydrothermal synthesis at 95/spl deg/C on laminated titanium foils. The films grown on Titanium foils were subsequently treated with oxygen plasma to improve the yield and reduce the dielectric loss. The films were characterized systematically using X-Ray Diffraction analysis, SEM and capacitance measurements. Films synthesized on thinner foils revealed nanograins under SEM and upon treating in oxygen plasma demonstrated dielectric loss of 0.06 at 100 kHz, which is the lowest loss reported on hydrothermal films synthesized at these temperatures. The effect of titanium source, hydrothermal conditions and the post hydrothermal treatment on the dielectric constant and loss of the synthesized films is discussed. Films with capacitance of more than 1.5 /spl mu/F/cm/sup 2/ and thickness of 300 nm (corresponding to a dielectric constant of above 350) were integrated into standard Printed Wiring Board processes using Ti foil lamination, patterning, hydrothermal treatment and electroless plating of copper for top metallization. These films are suitable candidate materials for digital decoupling applications.

Development of high performance interfill materials for system chips technology

Abstract: An innovative precisely interconnected chip (PIC) technology is currently under development at IBM to seek more effective means of creating system chips. The objective of this research is developing fabrication methods to permit the realization of high yielding large area chips, as well as chips that may contain very diverse technologies. This paper reports the use of a high-performance interfill material based on epoxy resin, which is used to connect the different chip sector macros that make up the system chip. This novel interfill material remains thermally stable through the subsequent processing temperature hierarchies during the interchip interconnection fabrication. Spherical SiO/sub 2/ powders are incorporated into the epoxy resin to improve its mechanical properties, reduce coefficient of thermal expansion, and increase thermal conductivity. Adhesion and rheology of the formulated interfill materials are evaluated. Microstructure of SiO/sub 2/ filled epoxy system is also investigated to confirm the reliability of the composite before and after thermal aging. Initial results indicate that the formulated EPOXY A resin composite is qualified for the system chip manufacturing process in terms of the dispensing processability, structural and mechanical integrity, and reliability.

Reliability assessment of high density multi-layer board assembly using shadow Moire and luminescence spectroscopy

Abstract: Novel low CTE-high stiffness organic and inorganic boards were evaluated for flip-chip on board technology without underfill. Standard liquid-liquid thermal shock tests were carried out on test vehicles with different board materials and failure modes were characterized. In-situ warpage and stress measurements were made to analyze the observed failure modes and to set guidelines for optimal board material selection. The effect of interlayer dielectric thickness on the package reliability has also been studied. The reliability test results are in accordance with the inferences from the in-situ warpage and stress measurements and it can be concluded that along with low CTE, high modulus is an inevitable substrate property requirement for flip-chip reliability without underfill in next-generation packages. This paper also presents photostimulated luminescence spectroscopy as a nondestructive and direct technique for the in-situ stress measurement in microsystems and thus a powerful means for reliability assessment.