Showing papers by "Rao Tummala published in 2005"

Packaging: past, present and future

Abstract: In the past, microsystems packaging played two roles: 1) It provided I/O connections to and from devices, referred to as IC or wafer level packaging, and 2) It interconnected both active and passive components on system level boards, referred to as systems packaging. Both were accomplished by interconnections or multilayer wiring at the package or board level. More recently, the IC devices have begun to integrate not only more and more transistors but also active and passive components on an individual chip, leading the community to believe that someday there may be a single-chip system, referred to as SOC or system-on-chip. This can be called horizontal or 2D integration of IC blocks toward systems. The community began to realize, however, that such an approach presents fundamental, engineering and investment limits and computing and integration limits for wireless and wired communication systems over the long run. This led to 3-D packaging approaches, often referred to as SIP or system-in-package. The SIP, while providing major opportunities in both miniaturization and integration for advanced and portable electronic products, is limited by the CMOS process just like the SOC. Some existing and emerging applications, however, include sensors, memory modules and embedded processors with DRAMs. More recent 3-D solutions, which incorporate stacked package approaches, offer solutions towards faster time-to-market and business impediments that have plagued MCM deployment for the past decade. There is a new concept which is called SOP or system-on-package. With SOP, Wit package, not the board, is the system. As such, SOP is beginning to address the shortcomings of both SOC and SIP, as well as traditional packaging which is bulky, costly, and lower in performance and reliability than ICs, in two ways: It uses CMOS-based Si for what it is good for, namely, for transistor integration, and the package, for what it is good for, namely, RF, optical and digital integration by means of IC-package-system co-design. The SOP package, therefore, overcomes both the computing limitations and integration limitations of SOC, SIP, MCM and traditional system packaging. It does this by having global wiring as well as RF, digital and optical component integration in the package, not in the chip. SOP, therefore, includes both active and passive components including embedded digital, RF and

Mid frequency decoupling using embedded decoupling capacitors

Abstract: Surface mount technology (SMT) decoupling capacitors fail to provide decoupling above 100MHz. This paper presents the use of embedded thin film capacitors to provide decoupling in the mid frequency range from 100MHz to 2GHz. On-chip capacitance provides decoupling above 2GHz. The effect of chip, package and board capacitors on the performance of digital systems is analyzed taking into account the parasitic effects of power/ground planes, vias and solder balls. A synthesis and selection methodology for embedded package capacitors is also presented.

Nanoindentation of single crystal and polycrystalline copper nanowires

Abstract: Metal nanowires are attracting considerable interest because of their potential importance to the technology of miniaturization of electronic devices in need of metallic contacts. One of the important attributes of nanowires is their potentially high mechanical strength. Nanoindentation is the most realistic tool at the present time to determine the mechanical properties of nanowires. The load-displacement behavior during nanoindentation of electrodeposited single crystal and 500 nm diameter polycrystalline copper nanowires was performed and the results are reported in this paper. The behavior has also been compared with that of bulk nanocrystalline and annealed copper. The hardness values for 50 nm grain size polycrystalline nanowires and those of extruded bulk 50 nm grain size copper were comparable, 2.1 GPa, and that of a 50 nm single crystal copper nanowire was 1.8 GPa.

Magnetic nanocomposites for organic compatible miniaturized antennas and inductors

Abstract: Current wireless systems are limited by RF technologies in their size, communication range, efficiency and cost. RF circuits are difficult to miniaturize without compromising performance. Antennas and inductors are major impediments for system miniaturization because of the lack of magnetic materials with suitable high frequency properties. Keeping antenna and inductor requirements into consideration, two magnetic nanocomposite systems - silica coated cobalt-BCB and Ni ferrite-epoxy were investigated as candidate materials. Nanocomposite thick film structures (125-225 microns) were screen printed onto organic substrates. Parallel plate capacitors and single coil coplanar inductors were fabricated on these films to characterize the electrical and magnetic properties of these materials at low and high frequencies. Electrical characterization showed that the Co/SiO/sub 2/ nanocomposite sample has a permeability and a matching permittivity of /spl sim/10 at GHz frequency range making it a good antenna candidate. Both polymer matrix composites retain high permeability at 1-2 GHz.

Embedded decoupling capacitor performance in high speed circuits

Abstract: Embedded decoupling is normally considered a better solution than surface mount decoupling for suppressing the switching noise of a high speed digital board/package because of its shorter leads that result in smaller parasitic inductance. This leads to lower impedance over a higher frequency band. It is presumably better in reliability and lowers the cost as well. Designers tend to use large value capacitors for efficient decoupling. Usually, to increase capacitance of an embedded capacitor, one can use a material with higher dielectric constant, design larger electrodes, and reduce the thickness of the dielectric. However, these strategies may sometimes lead to lower performance at high frequency band. This paper will discuss the pros and cons of different embedded capacitor approaches through simulation. As an application example, a typical power/ground network with an embedded capacitor will be compared with that of surface mount discrete capacitor.

Design, modeling and characterization of embedded capacitor networks for mid-frequency decoupling in semiconductor systems

Abstract: Embedded passives are gaining in importance due to the reduction in size of consumer electronic products. Among the passives, capacitors pose the biggest challenge due to the large capacitance required for decoupling high performance circuits. This paper focuses on the characterization and modeling of embedded capacitors. Design and modeling of embedded capacitor networks for decoupling semiconductor systems in the mid-frequency band (100 MHz to 2 GHz) will be highlighted in this paper

50 Micron Pitch Wafer Level Packaging Testbed with Reworkable IC-Package Nano Interconnects

Abstract: The decrease in feature sizes of micro-electronic devices has underlined the need for higher number of I/O's in order to increase its functionality. Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nanoscale devices. This will spur greater interest in developing electronic packages with fine and ultra fine pitches (20-50 microns). Current approaches for chip to package interconnections are limited in terms of either pitch or electrical-mechanical trade-off in properties. For example, lead free solder interconnects fail mechanically as the pitch is brought down from current 200 micron pitch to 20 micron. Compliant leads, on the other hand, solve mechanical reliability but at the expense of electrical performance. We propose reworkable nano interconnects as a new interconnect paradigm for potential low cost, highest performance and reliability—not trading one for the other. This paper describes the design and fabrication of the first 50 micron pitch wafer level packaging test bed to demonstrate reworkable nano-interconnects. Nano-grained electroplated copper is chosen as the primary interconnect material. Reworkability was addressed by a thin, liquid lead-free solder interface between the interconnect and the package. The processing approaches for the electroplated Cu interconnect, Sn-Cu interface and the high-density substrate wiring are presented along with the simulated mechanical and electrical performance of the interconnects.

Packaging of multi-core microprocessors: tradeoffs and potential solutions

Abstract: Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers and microprocessors. In this paper we propose to use a multicore processor approach to improve the performance of a processor. This paper discusses an analysis of the performance trade offs between single and multicore processors based on power, frequency, bandwidth and the role of embedded passives with high density wiring in future packages to support such processors.

Lead-free bonding systems

Abstract: Nano-structured interconnect formation and a reworkable bonding process using solder films Large area fabrication of nano-structured interconnects is demonstrated at a very fine pitch This technology can be used for pushing the limits of current flip chip bonding in terms of pitch, number of I/Os, superior combination of electrical and mechanical properties as well as reworkability Sol-gel and electroless processes were developed to demonstrate film bonding interfaces between metallic pads and nano interconnects Solution-derived nano-solder technology is an attractive low-cost method for several applications such as MEMS hermetic packaging, compliant interconnect bonding and bump-less nano-interconnects

Advances in high density interconnect substrate and printed wiring board technology

Abstract: The substrate or printed wiring board (PWB), as the largest component in electronic packages and systems, is performing an increasingly critical role in advanced packages, high performance electronic systems, and system-on-package (SOP) This paper reviews the advances of technologies of high density interconnect substrates and PWBs, and demonstrates technology developments of small and reliable microvia and stacked via that matches the high pin counts and fine pitch area array flip chip for needs of the year 2009 The paper also reviews breakthrough copper wiring density of line width and spaces less than 10 micron to route 4 rows in a 100 micron pitch With this technology it is possible to realize the target of semiconductor roadmap by the year of 2009 to route 4,600 I/Os to the inner layers by designing 1+n+1 structure

Design, simulation and measurement techniques for embedded decoupling capacitors in multi-GHz packages/PCBs

Abstract: Embedded capacitor is a better solution than surface mount capacitors for decoupling in a high speed, high performance packages/PCBs Our study has showed that with conventional approaches, the embedded capacitor for decoupling in power delivering network can work from 100 MHz to 1 GHz systems Pushing the operating frequency over 1 GHz is a challenge for system designers This paper discusses the embedded decoupling capacitor design for multi-GHz systems through principles, simulation, measurement error, and error elimination

High-density, end-to-end optoelectronic integration and packaging for digital-optical interconnect systems

Abstract: Recent progress toward implementing high-density, optical-digital building blocks necessary to accomplish efficient, end-to-end optical interconnect architecture on low cost FR-4 boards has been demonstrated. The optical interconnect system consists of fabricating an optical buffer layer separating board metallurgy from the optical lightwave circuit layer, and implementing optical links between embedded lasers and detectors. We will show an example of 1310 nm light from an edge emitting distributed-feedback or Fabry-Perot laser operating at 10 Gb/s being guided to the photodetector by a polymer waveguide. Both lasers and detector are embedded in the waveguide and all construction is built on a low-cost FR-4 board with 3 levels of metallurgy.

Warpage-induced lithographic limitations of FR-4 and the need for novel board materials for future microvia and global interconnect needs

Abstract: The effect of warpage on lithographic capabilities of organic circuit boards with multilayered thin film buildup was investigated. Two to six epoxy layers were built on various candidate boards to characterize the warpage and correlate it with analytical models. Underlying mechanisms were investigated and novel parameters defined to correlate warpage with photodefinition of ultrafine lines and vias on the board. Based on the experiments, warpage specifications for the multifunctional multilayered requirements in a proposed system-on-package (SOP) structure were defined. Experimentally validated FEM models were used to estimate the warpage during the multilayered buildup. Results show that FR-4 is not suitable for future high-density packaging needs and underscore the need for stiffer ceramic-based circuit board materials as replacement for FR-4

Recent Advances in Ceramic Composite Substrate Materials for High-Density and High Reliability Packaging Applications

Abstract: This paper reports the evaluation of novel large-area Carbon-Silicon Carbide (C-SiC) based composite board material that has the advantages of organic boards in terms of large-area processability and machinability at potentially lowcost while retaining the high stiffness (>250GPa) and Simatched CTE (~2.5ppm/°C) of ceramics. In this work test vehicles were fabricated using C-SiC boards for assessing ultra-fine pitch solder joint reliability without underfill as well as the reliability of high-density wiring on the board. Finite element models were developed to simulate the thermomechanical behavior of test vehicles. From finite-element simulations as well as thermal-shock reliability tests, it was observed that high-stiffness low-CTE C-SiC boards do not show any premature solder-joint fatigue failure or dielectric cracking. Furthermore, the C-SiC boards show minimal via-pad misalignment supporting the multilayer build-up structure required to achieve very high wiring density. The modeling and experimental results suggest that the novel low-cost large-area ceramic matrix composite (CSiC) has required thermomechanical properties, and is therefore a promising candidate substrate material for nextgeneration microsystems.

Design, fabrication, and reliability assessment of embedded resistors and capacitors on multilayered organic substrates

Abstract: Embedded passives provide a practical solution to microelectronics miniaturization. In a typical circuit, over 80 percent of the electronic components are passives such as resistors, inductors, and capacitors that could take up to 50 percent of the entire printed circuit board area. By integrating passive components within the substrate, embedded passives reduce the system real estate, eliminate the need for discrete components and assembly of same, enhance electrical performance and reliability, and potentially reduce the overall cost. Moreover, it is lead free. Even with these advantages, embedded passive technology is at a relatively immature stage and more characterization and optimization are needed for practical applications leading to its commercialization. This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on multilayered microvia organic substrate. Two test vehicles focusing on resistors and capacitors have been designed and fabricated by Packaging Research Center (PRC) and Endicott Interconnect Technologies (EI). Resistors are carbon ink based polymer thick film (PTF) and NiCrAlSi, and capacitors are made with polymer/ceramic nanocomposite material. High frequency measurement of these capacitors was performed. Furthermore, reliability assessments of thermal shock and temperature humidity tests based on JED EC standards are presented.

Material characterization for nano wafer level packaging application

Abstract: As the feature size of integrated circuit (IC) packages needs to be decreased significantly, computational methods in conjunction with experimental data have been employed to study the mechanical issues, which have become a concern for the components reliability. In this paper, the issues associated with and experimental methods necessary to perform material characterization for nano-wafer level packaging application will be investigated. Firstly, the need for nano-indentation to accurately characterize the modulus and hardness of copper thin film will be presented. Furthermore, some of the problems such as strain rate and thickness effects associated with extracting the modulus using nano-indentation will be addressed. Lastly, results from a fatigue experiment on a 200 /spl mu/m pitch solder column will also be given and factors affecting the failure criterion of these solder columns in fatigue conditions will be investigated.

Packaging of ZnO nanobelts as nanosensors: Synthesis, Alignment and Characterization

Abstract: One-dimensional ZnO nanobelt exhibits unique properties which makes it a perfect candidate for sensors in various applications In this paper, synthesis of ZnO nanobelts is described Design and fabrication of electrodes are presented Alignment of nanobelts, which is assisted by the optimized designed electrode, is discussed Dramatic improvement of the contact resistance is found after the sample is annealed at 500degC for 1 min This work lays the foundation for further fabrication, fictionalization and packaging of ZnO nanobelt based sensors

Variable embedded capacitor for active systems packaging

Abstract: Embedded systems play a crucial role is achieving very high component density and functions. Embedded actives have been the focus for three most important paradigms in systems integration. The paradigms are system in a package (SIP), system on a package (SOP) and system on a chip (SOC). ITRS road map requires very high component density by the year 2007. Embedded passives play an important role in determining frequency stability and signal integrity. Their stability depends on design, choice of material and process. There are limitations in achieving accurate parameters in the passives. Embedded passives have non reversible function or reworkability. These needs require techniques and process developed to have controlled actives which can change its parameters in a combination of mechanical, electrical and material properties. Flip chips are assembled on substrates enable thermal management. The need to mount several chip in unit area drives assembly process to wafer level chip stacking. There is need for embedded techniques to achieve good process for variable capacitors, resistors and inductors along with embedded flip chips. In this paper, we characterized the performance of a novel embedded variable capacitor fabricated using a polymer dielectric material, with one metal electrode fabricated on a low strength back plane to allow the electrode to flex. Sol-gel process is selected as it is a versatile technology to produce fine powders, fibers, coatings and is expected to yield highly homogeneous thin/thick films. A variable DC current is applied on the piezoelectric material to deform the dielectric, thereby changing the capacitance thus allowing the dielectric to behave as a variable capacitor. The compression effect on the dielectric also causes a thickness variation there by making the already submicron thick dielectric vary in thickness. The thinner dielectric makes it suitable for high frequency capacitance application. By changing the thickness of the dielectric and varying the frequency, the capacitor becomes very suitable to work over a broad range of frequencies and capacitances. The characteristics including material components and construction, dielectric properties and topography at metal-dielectric interfaces are optimized for a wide frequency band width. Attention is given to frequency dependence of the different material properties. Effects of the material characteristics on electrical performance, including capacitance are examined. Finally, processing and fabrication issues are discussed.

SOP Embedded Thin Film Resistors on High and Low Loss Thin Film Dielectrics

Abstract: This paper describes low-cost materials and processes for embedded thin film resistors that can be integrated into printed wiring board using sequential build-up processes. Realization of embedded resistors on conventional board level high loss epoxy (∼0.015 at 1 GHz) and proposed low loss BCB dielectric (∼0.0008 at > 40 GHz) has been explored in this study. Foil transfer and electroless plating have been attempted for embedding thin film resistors. Ni-P alloys were plated using conventional electroless plating, and NiCr and NiCrAlSi foils were used for the foil transfer process. A test vehicle consisting of various geometry and values of resistors was designed and fabricated to evaluate electrical and mechanical reliability of embedded thin film resistors. For the first time, Benzocyclobutene (BCB) has been proposed as a board level dielectric for advanced System-on-Package (SOP) module primarily due to its attractive low-loss (for RF application) and thin film (for high density wiring) properties. To realize embedded resistors on multi-layer BCB, a low-cost large format electroless process for deposition of NiP and NiWP thin film resistors using both low- (25°C) and high-temperature (90°C) baths has been developed. The electroless process exhibits uniform resistor thickness in the sub-micron range and offers low profile and excellent adhesion to BCB dielectric. These films also act as a seed layer for the subsequent direct electroplating of copper traces. NiP alloys can also be tailored to variable temperature coefficient of resistance (TCR) with different alloy compositions. The electroless process can be adopted in the PCB manufacturing industries with no additional investment.© 2005 ASME