Showing papers by "Rao Tummala published in 2007"

Vertically aligned Zn2SiO4 nanotube/ZnO nanowire heterojunction arrays.

Abstract: One-dimensional (1D) semiconductor nanostructures are important building blocks for achieving active nanophotonics and nanoelectronics. For example, semiconductor nanowires show great promise for waveguides, nanoelectronic devices, and integrated nanosystems because they can function both as device components for logic, memory, and sensing applications and as interconnects. So far, light-emitting diodes, lasers, photodetectors, and field-effect transistors have been fabricated using semiconductor nanowires. Semiconductor heterostructures 7] have played an important role in modern device physics because of their great importance to fundamental research and practical optoelectronic devices. Unique optical electronic devices, such as single-electron transistorsand resonant tunneling diodes, have been constructed based on such heterojunctions between two semiconductors. However, compared to the significant progress in homogeneous nanowires and nanotube preparation, a general synthetic scheme for 1D nanostructure heterojunctions is still lacking. Recently, axial semiconductor heterojunctions with composition modulations have been prepared based on controlled chemical vapor deposition of GaAs/GaP, InAs/InP, Si/SiGe, and ZnO/ ZnMgO systems. It has been recognized that the vertically aligned growth of 1D nanostructures is a simple but very efficient self-assembly technique for integrating nanowires into nanodevices. It is of great importance that those hetero-nanostructures can be directly fabricated with aligned morphology while keeping their unique structure and functions. In this study, we have for the first time been able to prepare aligned Zn2SiO4 nanotube/ZnO nanowire heterojunction arrays using a template-assisted growth, followed by an annealing process. The formation of the heterojunction is controlled by the annealing temperature and the size of the ZnO nanowire templates. The technique developed in this paper provides a potential technique for fabricating aligned heterojunction arrays. The synthesis strategy of the Zn2SiO4 nanotube/ZnO nanowire heterojunction arrays involved three steps. First, vertical aligned ZnO nanowire arrays were grown on GaN substrates via a vapor–liquid–solid (VLS) process. Second, an amorphous Si layer was deposited on the surface of the ZnO nanowire arrays by plasma-enhanced chemical vapor deposition (PECVD) to form ZnO/Si core/shell nanowire arrays (see Supporting Information). Finally, these arrays were annealed in an argon atmosphere at 800 8C for 10 h, then at 900 8C for 5 h, to obtain Zn2SiO4 nanotube/ZnO nanowire heterojunction arrays. Figure 1a shows a 308-tilted scanning electron microscopy (SEM) image of the vertical aligned ZnO nanowire array template, revealing that the ZnO nanowires had an average length of 8 mm, and the diameters were in the range of 50–500 nm. The typical morphology of the Zn2SiO4 nanotube/ZnO nanowire heterojunction arrays is shown in Figure 1b (308-tilted SEM image). The heterostructure exhibited almost the same average length as the ZnO nanowire template. The bottom region of the heterojunctions was very rough, and typically the top region of the heterojunctions had a larger diameter than the bottom region. Figure 1c shows the X-ray diffraction (XRD) pattern of the ZnO nanowire arrays (lower pattern) and the Zn2SiO4 nanotube/ZnO nanowire heterojunction arrays (upper pattern). Besides the peaks from the substrate, only diffraction from the (0002) and (0004) atomic planes of ZnO are observed from the ZnO nanowire template, indicating a perfect alignment. Compared to this XRD pattern, two new diffraction peaks were observed from the heterostructures. They were indexed as the (011) and (013) atomic planes of the orthorhombic structured Zn2SiO4 (JCPDS card 24-1469: a=0.574 nm, b=1.1504 nm, c=0.8395 nm), respectively. The detailed morphology and the chemical composition of the Zn2SiO4 nanotube/ZnO nanowire heterojunction were characterized by transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDX). Figure 2a shows a low-magnification TEM image of two [*] J. Liu, Dr. X. Wang, J. Song, Prof. Z. L. Wang School of Materials Science and Engineering Georgia Institute of Technology Atlanta, GA 30332-0245 (USA) Fax: (+1)404-894-8008 E-mail: zhong.wang@mse.gatech.edu

Chip-last Embedded Active for System-On-Package (SOP)

Abstract: Embedded active technology, in which thinned active chips are directly buried into a core or high-density-interconnect layers, is gaining more interest for ultra-miniaturization, increased functionality and better performance of SOP (system-on-package). In this study, chip-last embedded active concept is proposed to address some of process and reliability issues that current chip-first and chip-middle embedded active approaches have. The detailed process development for the first prototype of chip-last embedded active is described in this paper.

Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package

Abstract: Embedded passives are gaining in importance due to the reduction in size of electronic products. Capacitors pose the biggest challenge for integration in packages due to the large capacitance required for decoupling high performance circuits. Surface mount discrete (SMD) capacitors become ineffective charge providers above 100 MHz due to the increased effect of loop inductance. This paper focuses on the importance of embedded capacitors above this frequency. Modeling, measurements, and model to hardware correlation of these capacitors are shown. Design and modeling of embedded capacitor arrays for decoupling processors in the midfrequency band (100 MHz-2 GHz) is also highlighted in this paper.

Processing and Dielectric Properties of Nanocomposite Thin Film “Supercapacitors” for High-Frequency Embedded Decoupling

Abstract: The embedded decoupling capacitor problem has been pursued by several groups and industry around the world over the past decade. Currently, popular ceramic-polymer composites can only provide limited capacitance, typically within 10 nF/cm2 . With the reliability and processing constraints imposed, the capacitance density would be much lower. Newer capacitor concepts such as supercapacitors can overcome the limitations of existing polymer based capacitors and are now being considered. These concepts rely on nanostructured electrodes for high surface area per unit volume resulting in ultrahigh capacitance densities and unconventional polarization mechanisms such as electrical double layer and interfacial polarization. Supercapacitive structures lead to ultrahigh capacitance densities of the order of hundreds of microfarads. However, manufacturers report that the properties are unstable at high frequencies, typically even at tens of megahertz. To adapt these structures for mid-to-high-frequency decoupling, it is hence essential to systematically characterize the high-frequency dielectric properties of the thin nanocomposite films and nanostructured electrodes. This paper reports complete electrical characterization of a part of such a system, carbon black-epoxy nanocomposites. The high-frequency properties of the cured films were evaluated with a multiline calibration technique by measuring -parameters of transmission lines fabricated on the top of the dielectrics. Though the nanostructured carbon black epoxy composites showed high dielectric constant of 1000 at low frequencies, the high frequency (0.5-4.5GHz) dielectric constant was found to be only up to 10 times that of the base polymer matrix. The measured dielectric constant at gigahertz frequencies increased from 15-30 when the filler content was increased from 3.8% to 6.5%, with excessive leakage currents. Based on these measurements, conduction and polarization relaxation mechanisms will be assessed and the suitability of the thin film supercapacitors for high-frequency decoupling applications will be discussed.

Electrochemical Biosensors and Microfluidics in Organic System-on-Package Technology

Abstract: A nanobioelectronic system-on-package (SOP) with integrated electrochemical sensors, microfluidic channels and microneedles was demonstrated with organic compatible processes. A novel amperometric glucose sensor based on carbon nanotubes/glassy carbon working electrodes and glucose oxidase enzyme encapsulated in a sol-gel derived zirconia/nafion matrix was developed to demonstrate the biosensing. The sol-gel chemistry provides an attractive way to immobilize the sensitive biomolecules on the electrode at low temperatures. The amperometric measurements were carried out with a three-electrode system. SU8 epoxy based thick microfluidic channels were built over the electrode layer and then the enzyme was immobilized, followed by sealing of the channel with a PDMS membrane using a low temperature bonding process (60degC). The enzyme-catalyst reaction was recorded as the release of electrons from the oxidation of glucose into gluconolactone, hydrogen peroxide and subsequently into water. The results indicate that the response time is within few seconds. The current varied from 1 muA to 2.5 muA as the glucose concentration was increased from 5 mM to 20 mM. Finally, a compatible microneedle technology is demonstrated to enable transdermal fluid injection into the device for real-time health monitoring. Nanobio SOP with recent advances in nanobiosensing, nanomedicine, low-cost polymer-based high-density packaging, mixed-signal electronics can lead to the portable, reliable and cost effective biomedical devices of the future.

Integrating High-k Ceramic Thin Film Capacitors into Organic Substrates Via Low-Cost Solution Processing

Abstract: Current organic package-compatible embedded decoupling capacitors are based on thick film (8-16 m) polymer-ceramic composites with dielectric constant (k) of 20-30 and do not have sufficient capacitance density to meet the impedance requirements for emerging high-speed circuits and high power density microprocessors. High-k/high capacitance density ceramics films that can meet the performance targets are generally deposited by high-temperature processing or costly vacuum technology (radio frequency sputtering, PECVD) which are expensive and also incompatible with organic packages. The objective of this project is to develop ultra thin films (100-300nm) with high dielectric constant using organic compatible processes to meet future decoupling applications. In the current study, direct deposition of crystalline ceramic films on organic boards at temperatures less than 100C was demonstrated with the hydrothermal method. Post-hydrothermal treatments were shown to minimize the defects in the as-synthesized hydrothermal barium titanate films and improve the breakdown voltage (BDV) and leakage characteristics. Thin films with high capacitance densities and breakdown voltages of 10V were demonstrated. As an alternate technique, sol-gel technology was also demonstrated to integrate ceramic thin films in organic packages. A major barrier to synthesis of sol-gel films on copper foils is the process incompatibility of the sol-gel barium titanate with the copper electrodes. To enable process compatibility, process variables like sol pyrolysis temperature and time, and sintering conditions/atmosphere were optimized. Capacitance densities above 1.1F/cm was demonstrated on commercial copper foils with a BDV above 10 V. The two technologies reported in this study can potentially meet midfrequency decoupling requirements of digital systems.

Metal–Polymer Composite Interconnections for Ultra Fine-Pitch Wafer Level Packaging

Abstract: The decrease in feature sizes of microelectronic devices has underlined the need for higher number of input-outputs (I/Os) in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 mum). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This paper presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress composite structures for extremely fine-pitch wafer level packages. Analytical models for these structures justify the stress reduction at the interfaces and superior reliability as integrated circuit (IC)-package interconnects. Low coefficient of thermal expansion (CTE) polyimide structures with ultra-low stress, high toughness, and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80deg. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. This work also describes a selective electroless plating synthesis route to develop thin IC-package bonding interfaces with lead-free solder. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45degC. The lead-free solder composition was controlled by altering the plating bath formulation. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate using a standard reflow process. Metal-coated polymer structures in conjunction with the thin solder bonding films can provide low-cost high-performance solutions for wafer-level packaging.

Label-Free Protein Detection by ZnO Nanowire Based Bio-Sensors

Abstract: There is an increasing demand for portable, reliable, and cost effective bioelectronic systems for applications ranging from clinical diagnosis to homeland security. Conventional detection systems involve labeling the probe molecules, large amount of target molecules to enable detection, and elaborate signal transduction methods. Most of them also have to couple with optical detection equipments that are bulky and expensive. One dimensional (1-D) and two dimensional (2-D) structures such as nanowire, nanobelts and films are capable of detecting the molecular interactions in terms of significant change in their electrical properties leading to ultrahigh sensitivity and easy integration. In this paper, we demonstrate ZnO nanowires based bio-sesnors to detect IgG antibodies. Current-voltage (I-V) and Scanning Electron Microscopy (SEM) characterization were used to monitor the change in the conductivity as well as morphology. By comparing with the reference sample, the specific binding event between anti-IgG and IgG antibodies was detected. The data indicated a conductivity change by more than 12% after the protein hybridization. SEM images confirm the morphological change from reference samples to reacted samples. In addition, same experiment protocols are carried out for ZnO thin film devices. Similar change in I-V characteristics and morphologies are observed. Through this work, we have demonstrated to use ZnO nanowires as building blocks to fabricate bio-sensors which can potentially detect any protein. Conductimetric sensing results in a label-free detection system as it detects the protein hybridization events electrically. It is a cost effective process, which can be exploited further by expanding into arrays and integrating with microfluidics. When integrated on the SOP platform, this technology can lead to portable, reliable and cost effective biosensors with applications in many areas.

Hybrid Integration of End-to-End Optical Interconnects on Printed Circuit Boards

Abstract: This paper discusses the integration of an end-to-end optical interconnect testbed on printed circuit boards using inexpensive off-the-shelf, bare die, optoelectronic components. We developed a process for efficient and simultaneous in-plane optical coupling between edge emitting laser and waveguides, and between photodetector and waveguide. We demonstrated an optically smooth buffer layer separating the printed circuit layer from the optical transport layer. The demonstrated radically new optical interconnect technology, which we refer to as interface optical coupling, is able to efficiently and simultaneously form optical interfaces between waveguides, lasers and photodetectors by photolithographic technique, thereby eliminating the need for micro-lenses and manual alignment. The measured laser to waveguide coupling efficiency is 45% and measured waveguide to photodetector coupling is 35%. The optical link is demonstrated to operate at 10 Gbps.

Reliability of Nano-Structured Nickel Interconnections Replacing FlipChip Solder Assembly without Underfill

Abstract: This paper reports the reliability of fine pitch interconnections using nano-structured nickel as the primary interconnection material. Assembly was accomplished with different bonding methods to provide organic compatible low-temperature fabrication. Au-Sn and Sn-Cu were used for solder-based assembly of nanonickel interconnections. Low modulus conductive adhesives impart lower stresses in the interconnections and enhance reliability though they add electrical parasitics. These were used as an alternate bonding route and compared to solders. Test vehicles were fabricated at 200 micron pitch to evaluate the reliability with different bonding routes. Different CTE substrates - FR4 with 18 ppm/C, advanced organic boards with 10 ppm/C, novel low CTE (3 ppm/C) substrates based on carbon-silicon carbide (C-SiC) were evaluated. No underfilling was used in all the test vehicles evaluated in this study. High frequency electrical characterization was performed to compare the electrical parasitics from different bonding routes. Nanometal bumps bonded with conductive adhesives showed the highest reliability withstanding 1500 cycles. This technology can be easily downscaled to submicron and nanoscale unlike the current solder technologies leading to true nanointerconnections.

I/O Decoupling in High Speed Packages Using Embedded Planar Capacitors

Abstract: Embedded passives are gaining in importance due to the reduction in size of consumer electronic products. Embedded passives are gradually replacing discretes due to the miniaturization of electronic products. Integration of these passives within the package increases the real estate for active components. This would increase the functionality of the system. Among the passives, capacitors pose the biggest challenge due to the large capacitance required for decoupling high performance circuits. This paper will highlight the performance of DuPont's planar embedded capacitor laminates in organic packages to provide I/O decoupling for active circuits.

Reliability Modeling and Assessment of Embedded Capacitors in Organic Substrates

Abstract: Understanding and quantifying the RLC characteristics of the embedded passives under thermomechanical deformation during fabrication and accelerated thermal conditions is necessary for their successful implementation. Embedded passives are composite layers with dissimilar material properties compared to the neighboring layers in the integral substrate. The ongoing project explores the fabrication, multifield physics-based reliability modeling and accelerated testing of embedded passive test vehicles. As a first step, in this paper, the effect of thermomechanical deformation on the electrical characteristics of embedded capacitors is studied at frequencies from 100 KHz to 2 GHz using two test vehicles. Test vehicles with embedded passives were fabricated and were subjected to accelerated thermal cycles between -55degC to 125degC, between -40degC to 125degC and high humidity and temperature conditions of 85degC/85% RH. Significant changes in the electrical parameters of the embedded capacitors are observed. The fabrication process mechanics with multiphysics global-local modeling methodology is demonstrated to study the effect of thermal cycling on the electrical characteristics of embedded capacitors. The results obtained from the multiphysics global-local modeling methodology are validated against the measured electrical characteristics of the fabricated functional test boards. The effect of changes in electrical parameters of embedded passives on system performance of low-pass filters is presented

Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities

Abstract: Endless demands for digital convergence by ultra-miniaturization, increased functionality, better performance and low cost in both mobile and desktop systems are driving the needs for new and unique solutions in system integration. The requirements of future electronic systems include faster, smaller, lighter and thinner products. Advanced electronic packaging caters to these ultra-miniaturization and performance needs. The approach of embedding passive components has been in the fray for a while now and the relatively newer perspective to sustain the miniaturization trend efficiently is by embedded active chips as well. This paper discusses the electrical design aspects of embedded actives dealing with the chip-last methodology of embedding dies in particular. The various issues that are expected to surface are made clear through electromagnetic simulations using 3D solver tools. The transmission lines forming the substrate wiring when the cavities are made are analyzed comprehensively. A test vehicle is fabricated based on this new approach and preliminary measurement results are also included in this paper.

Capped Optical Polymeric Waveguide

Abstract: We present here a new type of polymer waveguides (i.e., capped waveguide) fabricated using contact photolithography with considerable performance improvement over the conventional waveguides. We also show that by simultaneous patterning of the core and the top cladding in capped waveguides, we can considerably reduce the effect of fabrication defects and reduce the propagation loss by at least 20% compared to conventional waveguides.

Multi-layer Copper-Dielectric Adhesion Challenges of 5-12 micron Lines/Spaces for Next Generation SOP (System-on-Package) / Microprocessor Package Substrates

Abstract: System-on-package (SOP) is a highly integrated systems packaging technology for convergent computing, communication, consumer, and bio-electronic functions in a single package or module. SOP aims to miniaturize systems by the integration of system-level components at microscale in the short term and nanoscale in the future. A key challenge for active and passive component integration is the demand for additional fine pitch wiring in the substrate for interconnecting these thin film embedded components. This adds to the already escalating need for high wiring density substrates driven by transistor density on the IC (Moore's Law). This paper addresses a critical process technology for SOP/microprocessor ultra-high density organic build-up substrates, namely, surface treatment of copper and dielectric in multilayer wiring. This process is critical for the challenges of processing and maintaining signal integrity at lines and spaces below 12 mum. A complete description of fine line and space fabrication and a novel copper adhesion process and its operating parameters are presented. We demonstrate this process with superior bonding strength through accelerated reliability testing. Results are shown not only state-of-the-art build-up films but also for high-performance substrates and prepregs in comparison to more traditional copper roughening treatment methods.

Processing, Properties and Electrical Reliability of Embedded Ultra-Thin Film Ceramic Capacitors in Organic Packages

Abstract: Traditional ceramic thick films have served the need for decoupling applications but require too high a temperature processing to be embedded in organic packages. Copper foil compatible sol-gel-derived ferroelectric thin film integration addresses this problem due to its unique advantages such as the ability to precisely control the composition of the films, large-area manufacturability using simple and inexpensive equipment and ease of introducing dopants to engineer the dielectric properties like loss tangent and DC leakage characteristics. This paper presents synthesis, fabrication, electrical characterization and electrical reliability test of embedded ultra thin film (200-300nm) capacitors with capacitance density >2muF/cm2, low-loss, low leakage current and high breakdown voltage via sol-gel technology & foil lamination. Further, we investigated the effect of (i) smoothness of the foil and (ii) non-stochiometery on the microstructure as well as on the electrical properties of sol-gel barium titanate thin films on bare copper foil. The capacitance densities, leakage characteristics and electrical reliability data demonstrate the suitability of this technology for future embedded decoupling capacitor applications.

Fine Line Photolithography and Ultra High Density Package Substrate for Next Generation System-on-Package (SOP)

Abstract: Rapid changes will continue in the trend toward system integration and microminiaturization. System-on-a package (SOP) is a highly integrated packaging solution based on embedding thin film passive and active components in ultra high density build-up substrates. The SOP-substrate provides a platform leading to system multi-functional and microminiaturization which demands additional wiring capability for routing chips and interconnecting embedded components. Fine line photolithography with I-line UV light is the key enabling technology to achieve the required wiring density on substrate at low cost. We have studied the fundamentals of fine image transfer by I-line photolithography based on proximity exposure. The relationship of achievable minimum feature size and gap distance between photo-mask and photo resist was investigated by calculations and experiments. Calculation showed that as fine as 2 mum line and space could be achievable on an 8 mum thick photo resist at gap of zero. While experimental results showed that 6 mum line and space was obtained with gap of zero and 10 mum line and space was obtained at gap of 60 mum. 60 mum is the maximum gap for resolving sub-10 mum line and space by I-line photolithography. Fine line categories for package substrate and related technologies are summarized. Finally we demonstrate a build-up layer having extremely high wiring capability for 100 mum pitch area array flip chip with 3 copper routing lines per pitch and 1,600 bumps per layer for satisfying year 2010 semiconductor roadmap microprocessor requirements.

A novel electroless process for embedding a thin film resistor on the benzocyclobutene dielectric

Abstract: To realize embedded resistors on multilayer benzocyclobutene (BCB) either on-chip or on-board, a low-cost large format electroless process for deposition of NiP and NiWP thin-film resistors using both low-temperature (25°C) and high-temperature (90°C) baths has been developed. The electroless process exhibits uniform resistor thickness in the submicron range and offers low profile and excellent adhesion to the BCB dielectric layer. The resistor films also act as a seed layer for direct electroplating of copper traces. The NiP alloys can also be tailored to a variable temperature coefficient of resistance (TCR) with different alloy compositions. The electroless process can be adopted in the PCB manufacturing industries with no additional investment. This article is the first report on electroless plated thin film resistors on low loss BCB dielectric.

Lead-Free Solder Films Via Novel Solution Synthesis Routes

Abstract: We report two novel routes, sol-gel and electroless plating, for the synthesis of lead-free solders. Novel processes with these routes were developed and demonstrated for Sn-Ag-Cu, Sn-Ag systems to achieve thin bonding layers for assembly of fine pitch integrated circuits onto substrates. Sol-gel route can be used to accurately control the final alloy composition and incorporate additives leading to the designed thermomechanical properties. In this process, the inorganic polymer solutions were spin coated and then heat-treated in a reducing atmosphere to form thin films of lead-free solders. The presence of Ag and Cu enabled easy reduction of tin oxide to tin at 400degC that was not possible with Sn precursor. With the alternate solution reduction (electroless plating) approach, bonding layers can be deposited at almost room temperatures directly on organic substrates. With this approach, the deposition selectively occurs on the metal bonding pads, which eliminates the need for any lithography. Using this approach, electroless Sn-Ag films were demonstrated on organic laminates. These thin film synthesis routes can enable short interconnections that are critical for high density, high frequency, and embedded active component packaging.

A Real Time Precision Measurement Technique for Low Loss Optical Polymeric Waveguide

Abstract: Optical polymer waveguide is a key passive component for the optical interconnection. Design and fabrication of high performance waveguides has a critical importance for the success of optoelectronic integration. We present here a fast, non-destructive, sensitive, and real-time technique for detailed investigation of the propagation properties of planar optical waveguides. We use this technique to have demonstrated high performance polymer waveguides on PCB substrates with propagation loss less than 0.05 dB/cm. To the best of our knowledge, this was in the lowest loss date range reported for polymer waveguides on PCB substrates to date. A high sensitive CCD camera with a built-in integration function is utilized to observe the light streak in two dimensions through a two lens imaging system. A few seconds to a few ten seconds depends on the beam scattering intensity is needed for complete one measurement, compared to the sliding prism method requiring several hours and cutback method requiring even longer time. This technique can not only be used to evaluate the overall performance of a waveguide but also local waveguide performance and in-situ investigation of the propagation properties (defect effect, mode profile, bending properties, etc.). It can be extended to monitor the process of waveguide fabrication and alignment control during the assembly for the optical circuit integration.

Organic-Based RF Capacitors with Ceramic-Like Properties

Abstract: RF capacitor applications for filtering and signal matching need stringent tolerances in Temperature Coefficient of Capacitance (TCC) and Quality factor (Q). In this paper, the temperature dependence of the dielectric properties of polymer-ceramic composites was discussed, with particular emphasis on high Q polymers and paraelectric ceramic particles. This includes the important role of ceramic paraelectric particles such as A12O3, SiO2, Ta2O5 etc. as ceramic fillers and high Q polymers such as benzocyclobutene (BCB) in the development of high Q and low TCC dielectrics for embedded RF capacitors. High Q polymer by itself showed a negative TCC of about -250 ppm/ degC but the composite approach with A12O3, SiO2 and Ta2O5 fillers improved the TCC to -190, -130, +20 ppm/ degC , respectively, between temperatures ranging from room temperature to 125degC. Liquid coatable high Q polymer-based composites with 3-4X improvement in dielectric constant and nearly-zero TCC of approximately within plusmn30 ppm/degC were developed with Ta2O5 as the inorganic filler. This effect can be ascribed to the TCC compensation between negative TCC of high Q polymer and the positive TCC of paraelectric ceramic particle selected. The distribution of the particles in the polymer matrix is also a crucial aspect of this application.

Novel Ceramic Composite Substrates for High-Density and High Reliability Packaging

Abstract: This paper presents the development and evaluation of a large-area carbon-silicon carbide (C-SiC) based composite board material that has the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (> 200 GPa) and Si-matched coefficient of thermal expansion (CTE) (~ 2.5 ppm/degC) of ceramics. Test vehicles were fabricated using C-SiC boards for assessing ultra-fine pitch solder joint reliability without underfill as well as the reliability of high-density wiring with microvias on the board. Finite element reliability models were developed to simulate the thermomechanical behavior of test vehicles. From the finite-element simulations as well as accelerated reliability tests, the high stiffness low-CTE C-SiC boards did not show any premature solder joint fatigue failure or dielectric cracking. Furthermore, the C-SiC boards show minimal via-pad misalignment and support the multilayer buildup structure required to achieve very high wiring density. The modeling and experimental results suggest that the low-cost large-area ceramic matrix composite (C-SiC) has superior thermomechanical properties, and is, therefore, a promising candidate substrate material for the emerging microelectronic systems.

Influence of Stress and Temperature on the Microstructure Stability of Nanocrystalline Materials

Abstract: It is well established that nanocrystalline materials have unique mechanical and electrical properties in comparison to their microcrystalline counterparts due to their reduced crystallite or grain size. Loss of these unique properties due to grain growth under the effect of high temperature and stress is a limitation to their use in many applications. Recently it has been proposed to use dopants (alloying elements) to reduce the driving force for grain boundary motion, leading to improved microstructural stability and resistance to deformation. Inclusion of dopants has been shown to alter properties of nanocrystalline materials, although their precise effect on mechanical and electrical properties is still unclear. In this brief review article, work done in the domain of stability of crystalline materials using dopants and their application in nanocrystalline materials is discussed. The importance of both experiment and molecular dynamics simulations is presented.

Conductimetric Detection of Protein and Cancer Cells with Oxide Nanosensors

Abstract: Semiconducting oxides are widely known and commercially applied for their gas sensing properties. However, biochemical sensing has mostly depended on optical and electrochemical techniques that are more cumbersome. This work investigates the biosensing characteristics of ZnO nanobelts and ZnO thin films. Zinc oxide thin film sensors showed changes in conductivity after protein functionalization with rabbit IgG and hybridization with anti-rabbit IgG. Conductivity changes were also measured after coating the oxides with MCF-7 cancer cells and its antibodies. In another set of experiments, ZnO nanobelts showed systematic conductivity changes with rabbit IgG protein hybridization. The experimental results in this paper indicate that the conductimetric properties of nano and thin film oxides can be sensitized to protein and cancer cell hybridization reactions. This technique can also be applied to certain other pathogen proteins or toxic proteins from the environment leading to low-cost miniaturized wireless biosensors.