Showing papers by "Rao Tummala published in 2008"

Carrier density and Schottky barrier on the performance of DC nanogenerator.

Abstract: By assembling a ZnO nanowire (NW) array based nanogenerator (NG) that is transparent to UV light, we have investigated the performance of the NG by tuning its carrier density and the characteristics of the Schottky barrier at the interface between the metal electrode and the NW. The formation of a Schottky diode at the interface is a must for the effective operation of the NG. UV light not only increases the carrier density in ZnO but also reduces the barrier height. A reduced barrier height greatly weakens the function of the barrier for preserving the piezoelectric potential in the NW for an extended period of time, resulting in little output current. An increased carrier density speeds up the rate at which the piezoelectric charges are screened/neutralized, but a very low carrier density prevents the flow of current through the NWs. Therefore, there is an optimum conductance of the NW for maximizing the output of the NG. Our study provides solid evidence to further prove the mechanism proposed for the ...

Toward high output-power nanogenerator

Abstract: In this paper, the factors that determine the power output of a piezoelectric nanowire (NW) nanogenerator (NG) have been analyzed. The output current is the sum of those contributed by all of the NWs while the output voltage is determined by the voltage generated by a single NW, the capacitance of the NW array and the system, and the contact resistance. By growing uniform ZnO NWs with diameters of ∼100nm and lengths of ∼5μm, the output current density and output voltage of the NG was improved to ∼8.3μA∕cm2 and 10mV, respectively, which are 20–30 times higher than that we previously reported. A power generation density of ∼83nW∕cm2 is achieved by using a single layer NW NG.

Numerical and Experimental Investigation of Thermomechanical Deformation in High-Aspect-Ratio Electroplated Through-Silicon Vias

Abstract: In this paper we present the numerical and experimental analysis of thermomechanical deformation in high-aspect-ratio copper electroplated through-silicon vias (TSVs), which were fabricated by deep reactive ion etching, thermal oxidation, and bottom-up electroplating processes. Later, these TSVs were subjected to thermal cyclic loading of 25-125°C. Due to the significant mismatch in the coefficients of thermal expansion of silicon and copper, thermomechanical stress was generated at the copper-silicon interface. Detailed investigation of this stress is of prime importance as it is one of the main root-causes behind the crack formation and dielectric delamination at the interface. A three-dimensional finite element model of the copper-filled TSVs was built and simulation was performed to predict the theoretical distribution of thermomechanical deformation. A noncontact digital image speckle correlation technique was used for the in situ measurement of the thermal deformation and the thermomechanical stress. Thermomechanical shear strain at the copper-silicon oxide-silicon interface was found to be the significant deformation mode in these TSVs.

Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors

Abstract: The performance of embedded planar capacitors in noise suppression of input/output (I/O) circuits and improvements in board impedance profile have been investigated in this paper. Simultaneous switching noise (SSN) is a critical issue in today's systems and this paper shows performance improvements by introducing thin planar embedded capacitors in the board stack up. Measurement and modeling results by including the effects of transmission lines and the power ground plane pairs in the board stack up in the gigahertz range quantify the performance of the embedded capacitors.

New 3-D Chip Stacking Architectures by Wire-On-Bump and Bump-On-Flex

Abstract: Two new 3-D chip stacking technologies, wire-on-bump (WOB) and bump-on-flex (BOF), are proposed and demonstrated with their prototypes. The WOB and BOF technologies are for low cost 3-D stacking of memory chips by vertical side interconnections with metal wires and flex-circuits, respectively. These new 3-D chip stacking technologies have benefits such as a shorter signal path and 3-D stackability of an unlimited number of chips compared to wire-bonded chip stacking. In the case of the BOF technology, additional active and passive components can be either surface-mounted onto or embedded into the flex-circuit, which is an added value that other chip stacking technologies have not demonstrated so far. More importantly, the WOB and BOF technologies enable lower cost processes than Si through-via technology, which is thus more suitable for memory chip stacking. This paper describes the detailed processes for our unique chip stacking structures with vertical interconnection methods of the WOB and BOF. Finite-element modeling and thermal cycle (TC) tests are also performed to address their thermo-mechanical reliability.

Real-time protein detection using ZnO nanowire/thin film bio-sensor integrated with microfluidic system

Abstract: A nanoscale semiconducting ZnO based biosensor with integrated microfluidics is designed, fabricated and tested to demonstrate the detection of streptavidin, a commonly used protein. Amperometric (I-t) measurement is utilized to detect the change of conductivity over time. By comparing with the control experiment, the specific binding event between biotin and streptavidin is detected. The data indicates a conductivity change by more than 20% after the protein hybridization. The second part of the papers presents a ZnO thin film based biosensor which is integated with a microfluidic system. Same experiment protocols are carried and similar change in I-t characteristics is observed. This is the first demonstration of real time biosensing with ZnO nanowires and thin films that are integrated with microfluidic systems. This can be further extended to fabricate bio-sensors which can potentially detect any protein in real time. Amperometric sensing results in a label-free detection system as it detects the protein hybridization events electrically. when integrated on the system-on-package (SOP) platform, this technology can lead to portable, reliable and cost effective biosensors with applications in many areas.

Ultra high Q embedded inductors in highly miniaturized family of low loss organic substrates

Abstract: This paper presents the design, fabrication and measurement of high Q miniaturized inductors on a new family of ultra thin organic substrates. This paper for the first time discusses the design and fabrication of embedding ultra miniaturized RF inductors in ultra thin (100 - 150 microns thickness) organic substrates. The substrate described in this paper belongs to a new family of ultra low profile organic laminates with a loss tangent of about 0.0034 - 0.0045 and a dielectric constant of 3.4. Innovative inductor designs on this ultra thin substrate resulted in unloaded quality factors of about 100 - 150 in the frequency range of 1- 15 GHz and have line widths in the range of 2 - 4 mils and occupying an area of 0.062 - 0.64 mm2. Design optimization, modeling and simulations performed are discussed in detail. Two test vehicles - test vehicle 1 (TV1) made up of two metal layers, having a thickness of 100 microns and test vehicle 2 (TV2), consisting of four metal layers and 150 microns in thickness have been used for the design of these inductors.

Thermomechanical Reliability of Nickel Pillar Interconnections Replacing Flip-Chip Solder Without Underfill

Abstract: Interconnect technologies between ICs and packages or boards have a significant impact on the IC performance and packaging density. Today, the interconnections are typically accomplished with either wire bonding or flip-chip solders. While both of these technologies are incremental, they also run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect might not satisfy the thermomechanical reliability requirements at very fine-pitches. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. This paper reports fine-pitch interconnection technologies using nano-structured nickel as primary interconnection material. The nano-grained nickels are produced by electroplating process. The primary nano-structured interconnects are assembled with different bonding methods to provide organic compatible low-temperature fabrication. Au-Sn and Sn-Cu are used for solder-based assembly of nano-nickel interconnections. Low modulus anisotropic conductive films (ACFs) are also used as an alternate bonding route of the solders. No underfilling is used in all the interconnect structures evaluated in this paper. Assembly are accomplished on different coefficient of thermal expansion (CTE) substrates including FR-4 with 18 ppm/degC, advanced organic substrates with 10 ppm/degC, novel low CTE (3 ppm/degC) substrates based on carbon-silicon carbide (C-SiC). The thermomechanical reliability of all the nano-interconnects assembled on different CTE substrates with different bonding approaches is evaluated by thermal shock testing and finite-element analysis. Nano-nickel interconnects bonded with the ACF showed the highest reliability withstanding 1500 cycles. In all cases, no apparent failure was observed in the primary nano-nickel metal interconnects. This technology is expected to be easily downscaled to submicrometer and nano-scale unlike the current solder technologies leading to true nano-interconnections.

Coupling noise analysis and high frequency design optimization of power/ground plane stack-up in embedded chip substrate cavities

Abstract: Future electronic systems demand faster, smaller, lighter and thinner products. Embedding active and passive components in package size boards is one of the major steps in accomplishing system level miniaturization and multifunctionality. All multifunctional system packages should pay attention to signal and power integrity for ensuring proper operation of the system. Predominant challenge encountered with respect to power integrity in mixed signal systems is coupling through the power distribution network. This coupling which is a form of noise affects power integrity if left unchecked, especially in case of embedded actives where there are large apertures (die sized) in the metal planes and cavities in dielectric to accommodate the chips. This paper for the first time brings out coupling noise analysis for different power/ground plane stack-ups in embedded chip substrate cavities.

Low-temperature, fine-pitch interconnections using self-patternable metallic nanoparticles as the bonding layer

Abstract: High speed digital and mixed signal applications are driving short and more reliable fine pitch interconnection with higher I/O count in 3D architectures. Thin film die to wafer and wafer to wafer bonding with copper-based interconnections have several benefits in terms of low cost, process compatibility with semiconductor infrastructure, and the shortest interconnection with the best electrical performance. However, the bonding is accomplished at around 400 C, with pressures exceeding 30 N/cm2 which may not be compatible with thinned dies, and in ultrahigh vacuum and cleanroom environments with careful copper oxide cleaning procedures. The bonding time is typically 1 hour, which also limits the throughput. The process windows are relatively narrow with several temperature compatibility issues. This paper deals with low temperature bonding process using high surface energy metallic nanoparticles such as copper and gold. Bonding is enhanced by accelerated diffusion kinetics. Self patterning technique has also been developed to assist fine pitch bonding. This is based on selective wetting or selective deposition of nanoparticles.

High performance organic dielectrics and high density substrates for next generation System on a Package (SOP) technology

Abstract: This paper introduces a new developmental family of thin film dielectric materials that have low dielectric constant (2.5 - 3.1 ) and low loss tangent (<0.005) at 10 GHz and discusses process development and reliability testing of a 1-2-1 substrate stack-up with versions of these high-performance developmental dielectrics (RXP-4). The variant used in these experiments is called RXP-4a. Various conditions were tried to optimize processing and reliability. Fine line structures down to 14 mum have been demonstrated. These were also found to pass reliability testing. Additionally, FE modeling was performed to understand the predicted reliability of microvias in these RXP-4 materials.

Development of Stretch Solder Interconnections for Wafer Level Packaging

Abstract: A wafer level packaging technique has been developed with an inherent advantage of good solder joint co-planarity suitable for wafer level testing. A suitable weak metallization scheme has also been established for the detachment process. During the fabrication process, the compliancy of the solder joint is enhanced through stretching to achieve a small shape factor. Thermal cycling reliability of these hourglass-shaped, stretch solder interconnections has been found to be considerably better than that of the conventional spherical-shaped solder bumps.

2008 IEEE electrical performance of electronic packaging suppression of vertical coupling using Electromagnetic Band Gap structures

Abstract: This paper for the first time demonstrates the use of electromagnetic band gap (EBG) structures for isolation between multiple plane pairs along the vertical direction. Planar EBG structures have been applied for the suppression of vertical noise coupling in the GHz range of frequencies. Simulation and measurement results showing good isolation in the stop bands of the EBGs are presented.

Nanogranular Magnetic Core Inductors: Design, Fabrication, and Packaging

Abstract: Technological advances often lead to a transition when the vision of the past no longer remains a vision and becomes the demand of the present. Miniaturized, cost-effective, and mega functional devices are the present day’s demand. With Moore’s law driving the miniaturization of active devices, passive components have been left behind. As the trend continues toward miniaturization, electronic industries are experiencing an immense demand for miniaturized and more efficient passive components.

Ferroelectrics and ferromagnetics for noise isolation in integrated circuits, packaging, and system architectures

Abstract: Disclosed are ferroelectric and ferromagnetic noise isolation structures that reduce electromagnetic interference and noise in integrated circuit devices and system architectures. Representative structures comprise two or more devices that are vertically disposed relative to one another, and a thin ferroelectric or ferromagnetic film layer disposed between the respective devices that isolates electromagnetic energy coupling from one device to another.

Low Temperature (≪100°C) deposited pyrochlore films with high capacitance (200 nF/cm 2 ), low loss (∼0.003) and low TCF (≪100 ppm/C) for integrating RF components

Abstract: We demonstrate polymer ceramic composites and pyrochlore based thin film capacitors for embedded RF capacitors. Unlike perovskites such as barium titanate, pyrochlores have low loss and stable properties with temperature and frequency while retaining a moderately high dielectric constant. Hence, these are ideally suited for RF capacitor components both as fillers in polymers and as ultrathin films. Unfortunately, pyrochlores are generally formed at above 400 C making them difficult for organic compatible integration either on BCB build-up layers on Si or traditional organic substrates. In this report, we report new energy irradiation processes that can form pyrochlores at temperatures less than 100 C. The process starts by depositing a thin layer of Ti by e- beam evaporation, followed by hydrothermally converting it to barium titanate. The film is then converted into a pyrochlore phase at less than 100 C by oxygen ion irradiation. The phase transformation results were confirmed with XRD and SEM. By a combination of wet chemical treatment followed by oxygen ion irradiation, this technique shows the feasibility of depositing a low TCC (<100 ppm/C), low loss (0.003-0.005) and high capacitance density film (200 nF/cm2) directly on plastic substrates at temperatures less than 100 C. The films show BDVs greater than 10 volts and adequate leakage current behavior that is suitable for biased RF circuits.

A novel method for suppression of vertical coupling in multi-layered substrates

Abstract: This paper demonstrates the suppression of vertical coupling between multiple plane pairs in GHz range of frequencies with electromagnetic band-gap structures (EBGs). For the first time, dispersion diagrams have been developed for the EBGs used in vertical isolation giving insight into the coupling suppression. Results from simulations, measurements and analytical methods are presented to demonstrate the proposed method.

A numerical analysis of crack growth and morphology evolution in chip-to-packages nano-interconnections

Abstract: The International Technology Roadmap for semiconductors (ITRS) has predicted that by the year 2007, integrated chip (IC) packages will contain feature sizes of 65 nm and an I/O pitch for the die-to-package interconnects approaching 80 mum. These will reduce even further in the next five years. The current approach of using surface mount technology and flip chip are mainly solder based and the lead and lead-free solder interconnects are known to fail mechanically as the pitch is reduced from 200 mum down to lower levels due to the thermal mismatch between the substrate and the chip. Although compliant interconnection could solve some of the mechanical issues, it is done at the expense of the electric performance. The PRC at Georgia Institute of Technology is proposing re-workable copper based nano-interconnections as a new interconnection paradigm as the next step beyond lead-free solders for future low-cost, high performance and high reliability packages. However, very limited data is published about the fatigue life of nano-crystalline materials and specifically those of nano-crystalline copper. It is important to predict crack growth as it can aid the understanding of the useful life of the IC-packages' interconnections. Multiple mechanisms may be responsible for crack initiation, but eventually most dominant fatigue cracks form a surface crack, which often have a semi-elliptical shape. Hence, the fatigue crack growth life predictions in this study are based on the assumption of elliptical and semi-elliptical cracks being initiated in the nano-interconnections. In this study, numerical analysis using the J-integral stress intensity parameter, in conjunction with experimental fatigue crack growth data, has been employed to study semi-elliptical crack growth and morphology evolution in nano-interconnection subject to uniaxial fatigue loading in linear-elastic conditions. The results indicate that a J-integral finite element analysis, using the loading portion of the fatigue cycle, in conjunction with known rates of fatigue crack growth can approximate surface crack morphology evolution. This study also predicts that the long crack growth is a relatively small portion of the total fatigue life of the material for the experimental LCF conditions. Hence, initiation of the cracks in the interconnection is the main criterion used to predict its fatigue life.

A Real-Time Precision Characterization Technique for Low-Loss Optical Polymeric Waveguide and Lightwave Circuits

Abstract: An optical polymer waveguide is a key passive component for the optical interconnection. Design, fabrication, and characterization of high-performance waveguides have critical importance for the success of optoelectronic integration. In addition, defect effects, coupling, leakages, crosstalk, etc. are great concerns for the lightwave circuits. We present herein a fast, nondestructive, sensitive, real-time technique for detailed investigation of the propagation properties of planar optical waveguides and lightwave circuits. We use this technique to measure low-loss polymer waveguides on printed circuit board (PCB) substrates, and we have measured propagation losses of 0.065 dB/cm at 850 nm and 0.046 dB/cm at 980 nm. To the best of our knowledge, these are among the lowest losses reported to date for polymer waveguides on PCB substrates. A high-sensitivity CCD camera with a built-in integration function is utilized to observe the light streak in two dimensions through a two-lens imaging system. A few second...

A non-destructive characterization and real time monitor technique for low-loss, polymeric waveguide circuits

Abstract: Optical polymer waveguide is a key passive component for the optical interconnection. Design, fabrication, and characterization of high performance waveguides have critical importance for the success of optoelectronic integration. In addition, defect effect, coupling, leakages and cross talk etc. are big concerns for the lightwave circuits. We present here a fast, non-destructive, sensitive, and real-time technique for detailed investigation of the propagation properties of planar optical waveguides and lightwave circuits. We use this technique to measure low loss polymer waveguides on printed circuit board (PCB) substrates and have measured the propagation loss of 0.065 dB/cm at 850 nm and 0.046 dB/cm at 980 nm. To the best of our knowledge, these are among the lowest loss data reported for polymer waveguides on PCB substrates to date. A high sensitive CCD camera with a built-in integration function is utilized to observe the light streak in two dimensions through a two lens imaging system. A few seconds to a few ten seconds is required for a complete measurement, compared to several hours for the sliding prism method and even longer for time cutback method. This technique can be used to evaluate not only the overall performance of a waveguide but also the local waveguide performance and the in-situ propagation properties (i.e., defect effect, bending effect, coupling and leakages, etc.). It can be extended to monitor the process of waveguide fabrication and alignment control during the assembly for the lightwave circuit integration.

Microwave design & characterization of a novel Nano-Cu based ultra-fine pitch chip-to-package interconnect

Abstract: This paper presents design and characterization of nano-Cu based ultra-fine pitch chip-to-package interconnects for microwave frequencies. Transitions are designed with this new interconnect and characterized up to 40 GHz in packaging configurations such as chip-on-chip and chip-on-package.