Showing papers by "Rao Tummala published in 2012"

Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

Abstract: Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization.

Low-cost and low-loss 3D silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC

Abstract: This paper presents the design, fabrication and electrical characterization of a low loss and low cost non-traditional silicon interposer, demonstrating the high bandwidth chip-to-chip interconnection capability of the 3D silicon interposer, with equivalent or better performance than 3D ICs with TSVs, at a much lower cost. This scalable approach uses thin polycrystalline silicon in wafer or panel form, forms lower cost through-package-vias (TPVs) at fine pitch by special high throughput laser processes. The electrical performance is improved by thick polymer liners within the TPVs. Double side package processes for TPV metallization and RDL layers using dry film polymers and plating leads to significant cost reduction compared to single side TSV and BEOL wafer processes. Combined loss of 3mm long CPW lines and two TPVs in the low loss silicon interposer was demonstrated at less than 1dB at 10GHz. The fine pitch TPV capability and low loss of this non-traditional silicon interposer leads to 3D interposers with double side chips interconnected at equivalent bandwidth to wide bus I/O 3D ICs at a much lower cost and with better testability, thermal management and scalability.

Highly-reliable silicon and glass interposers-to-printed wiring board SMT interconnections: Modeling, design, fabrication and reliability

Abstract: Ultra-miniaturization and 3D integration of electronic systems require interposers with high density of off-chip interconnections. Silicon and glass interposers are being developed widely to meet these needs. These substrate materials have the intrinsic advantage of very high dimensional stability over traditional organic substrates [1] thus providing opportunities for layer to layer wiring with very small vias. However, compared to organic boards, with a coefficient of thermal expansion (CTE) of about 12–18 ppm/°C, silicon and glass substrates have a significantly lower CTE of 3–8 ppm/°C. Therefore, reliability becomes one of the major concerns when silicon or glass interposers are mounted directly on organic system boards using SMT technology with solders. This paper presents an approach to address the above reliability issues using compliant build-up dielectrics to decouple the stress from interposer to the system board, to reduce the stress experienced by the solder interconnections. The proposed approach is compatible with surface mount technology (SMT) and also helps with the handling and metallization of thin silicon and glass substrates. Finite element modeling was used to analyze the effectiveness of the compliant dielectrics, laminated onto both sides of silicon or glass interposers. Parametric study was performed to analyze the influence of multiple variables, such as material properties and geometry parameters, on the reliability of the SMT interconnections, to optimize the buffering effect. Test vehicles of size 7.2mm × 7.2mm were fabricated with 25um thick RXP-4M polymer, laminated on both sides of glass and silicon interposers. In this study, interposers with 180um thick, low CTE glass, 180um thick high CTE glass, and 240um thick silicon interposers were fabricated and assembled on standard FR-4 system boards, using ball grid array (BGA) interconnections. Thermal cycling test was performed to investigate the reliability of solder ball joints. The high CTE glass sample was shown to survive 1900 thermal cycles from −55°C to 125°C, before the first failure was detected in one of the corner joints. This paper shows that the use of compliant dielectric material, explored in this research, yields promising reliability performance of BGA interconnections with low CTE interposers without underfill at a body size of 7.2mm.

Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages

Abstract: A thermo-mechanical reliability study of through-silicon vias (TSVs) is presented in this paper. TSVs are used to interconnect stacked dies to achieve 3-D packages. As the core of the TSV contains high coefficient of thermal expansion (CTE) copper surrounded by low-CTE SiO2 and Si materials, the thermo-mechanical reliability of TSVs is a concern. When dies with such TSVs are stacked and packaged, the presence of additional structures and associated materials could introduce different thermo-mechanical concerns compared with free-standing wafers. This paper presents 3-D finite-element models for studying the thermo-mechanical stresses in TSVs in free-standing wafers and in stacked dies, which are packaged. Warpage measurements have been used to validate the finite-element modeling approach. The results from the finite-element models show that the TSV stresses in a packaging configuration are typically lower than the TSV stresses in a free-standing wafer configuration. In addition, it is seen that the microbumps connecting adjacent dies experience high magnitude of inelastic strain, indicating that such locations are of reliability concern.

Chip-last embedded interconnect structures and methods of making the same

Abstract: CHIP-LAST EMBEDDED INTERCONNECT STRUCTURES AND METHODS OF MAKING THE SAME ABSTRACT The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

A low-cost approach to high-k thinfilm decoupling capacitors on silicon and glass interposers

Abstract: This paper demonstrates a novel low-cost thinfilm capacitor technology on silicon and glass interposers for decoupling in high-speed digital systems. Silicon interposers with thinfilm capacitors have been demonstrated before, but these technologies have not been widely adapted because of the high cost of platinum electrodes and their incompatibility with packaging infrastructure. Thinfilm capacitors with alternative package-compatible low-cost electrodes such as copper and nickel were unsuccessful because of the processing challenges on Si substrates that arise as a result of high inter-diffusion and film stress. A new class of solutions was explored to address the challenges on silicon interposer substrates. Glass-compatible crystallization processes were studied to achieve high capacitance densities. Nickel electrodes showed a capacitance density of 1.1 μF/cm2, 2–3× higher than those with alternative glass-compatible thinfilm capacitor technologies.

Application of Piezoresistive Stress Sensor in Wafer Bumping and Drop Impact Test of Embedded Ultrathin Device

Abstract: Though an understanding on the development of residual stresses in silicon device after chip level packaging processes has been investigated in previous studies, little is known about the development of stresses after wafer bumping process. In this paper, piezoresistive stress sensors were used to evaluate the stresses in device wafer after wafer bumping process, such as under bump metallization fabrication, dry-film process, and solder bumping. For the stress evaluation, n-type piezoresistive stress sensors were fabricated on p-type (100) silicon wafer and then sensors were calibrated to determine piezoresistive coefficients. The calibrated sensor wafers were finally used to measure residual in-plane stresses at the surface of device wafer. Due to the growing demand of portable and handheld devices, the reliability of electronic packages with Pb-free solder under drop impact condition has become an issue of concern. This paper aims to measure the real-time stress in an ultrathin die during a drop test to ascertain whether die cracking is a possible problem when dealing with 50-μm-thick dies. The advantages of these stress data are that they: 1) serve as a basis for process selection to meet the trends and needs of a reliable package, and for the development and improvement of existing processes; and 2) are important to enhance survivability during wafer bumping, handling and packaging.

Fabrication and characterization of novel silicon-compatible high-density capacitors

Abstract: System integration and miniaturization demands are driving component technologies towards integrated thin films with higher volumetric efficiencies and component densities. Among the various system components, achieving higher densities with capacitors, integrated in thin film form has been a major challenge for the past few decades. This paper reports the first proof-of-concept demonstration of a novel silicon-compatible high-density capacitor technology. The key novelty stems from the tremendous enhancement in surface area from thin and porous copper nanoelectrodes and conformal alumina dielectric on such nanoelectrodes. Atomic Layer Deposition was chosen as the dielectric process because of its self-limiting, defect-free and conformal deposition on 3-D structures. Alumina with its moderate permittivity and superior dielectric properties over large voltage ranges was employed as the representative dielectric. Thin copper particulate electrodes with conformal counter electrodes showed 10 times higher capacitance density compared to the planar devices, with similar leakage properties. Thicker electrodes showed enormous enhancement in surface area but inferior leakage properties. Combination of compositional and morphological techniques was used to show alumina conformality on complex 3-D structures of copper particulate electrode. Capacitance–Voltage and Current–Voltage characterizations were carried out to confirm the feasibility of the novel high density 3-D capacitor structure.

Through package via structures in panel-based silicon substrates and methods of making the same

Abstract: The various embodiments of the present invention provide a low cost, low electrical loss, and low stress panel-based silicon interposer with TPVs. The interposer of the present invention has a thickness of about 100 microns to 200 microns and such thickness is achieved without utilizing a carrier and further wherein no grinding, bonding, or debonding methods are utilized, therefore distinguishing the interposer of the present invention from prior art embodiments.

Chip-last embedded interconnect structures

Abstract: The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Magnetic devices utilizing nanocomposite films layered with adhesives

Abstract: Exemplary embodiments provide a nanomagnetic structure and method of making the same, comprising a device substrate, a plurality of nanomagnetic composite layers disposed on the device substrate, wherein an adhesive layer is interposed between each of the plurality of nanomagnetic composite layers. Metal windings are integrated within the plurality of nanomagnetic composite layers to form an inductor core, wherein the nanomagnetic structure has a thickness ranging from about 5 to about 100 microns.

High current-carrying and highly-reliable 30μm diameter Cu-Cu area-array interconnections without solder

Abstract: Innovative packaging technologies have delivered a remarkable generation of mobile devices, enabling the transition from simple single-function systems to advanced multifunctional computing and communication systems in the span of only a decade. Of many technology advancements, high interconnection (I/O) density has been a major contributing factor in this transition. However, the constant push for high I/O density has resulted in smaller pitch and interconnection dimensions, thereby introducing the concerns for thermo-mechanical reliability and electromigration resistance due to higher current density. Georgia Tech Packaging Research Center (GT-PRC) has been developing an ultra-fine pitch, copper-to-copper interconnection technology to overcome the limitations of current solder bump technology. This paper emphasizes the robustness of this interconnection technology by demonstrating its performance under high current density and high I/O area-array configuration. Already demonstrated at 30μm pitch, low profile copper-to-copper interconnections, developed at GT-PRC using a low-cost, low-temperature direct copper-to-copper bonding approach, have been shown [1–2] to have high reliability under thermal cycling test (TCT), high temperature storage (HTS) test and highly accelerated stress test (HAST). Utilized in the pioneering chip-last approach, this interconnection method has also been proven [3] ready for commercialization through a two-step high throughput multi-chip embedding process and three-dimensional stacking capability. This research demonstrates, for the first time, the ability of the aforementioned adhesive-bonded copper-to-copper interconnections to — (1) withstand 2000 thermal cycles in a high pin-count area-array configuration and (2) survive ∼800 hours of testing at 104–105 A/cm2 current density, which, to the best of authors' knowledge is the highest ever reported for adhesive based interconnections [4–6].

Nanomagnetics for High-Performance, Miniaturized Power, and RF Components [Nanopackaging]

Abstract: This article describes magnetic nanomaterials and the benefits they provide in system components using three examples-high-density inductors, antennas, and electromagnetic interference (EMI) isolation structures.

Highly Reliable and Manufacturable Ultrafine Pitch Cu–Cu Interconnections for Chip-Last Embedding With Chip-First Benefits

Abstract: Flip-chip packaging of Ultrafine pitch integrated circuits aggravates the stress-strain concerns as the interconnection pitch is decreased, requiring a fundamentally different system approach to interconnections, underfill processes and interfaces, and the substrate. This paper demonstrates an innovative and manufacturable solution to achieve excellent reliability at Ultrafine pitch (~30 μm) using direct copper-copper (Cu-Cu) interconnections with adhesives. A number of 30-μm bump pitch test vehicles (TVs) were designed with 3 mm × 3 mm chips to extract both daisy chain resistance and single-bump resistance data. Assembled bump resistivity was found to be ~ 3-4× lower than most solders. Performance of these TVs was studied for high temperature storage (HTS) life test, unbiased-highly accelerated stress test (U-HAST) and thermal cycling test (TCT). Test results showed that the assemblies with this next generation interconnection technology depicted excellent reliability results in HTS, U-HAST, and TCT tests. Based on these results, it is concluded that adhesive materials, provide unique opportunities for Ultrafine pitch and high performance interconnections.

High-density capacitors with conformal high-k dielectrics on etched-metal foils

Abstract: This paper describes the fabrication and characterization of high-density capacitors using etched-metal foils as high-surface area electrodes. High permittivity films were conformally-formed over the metal foils using an anodization reaction. The approach was demonstrated with two material systems, viz., etched aluminum foils and porous titanium foils. Both the metal anodizations were carried out with aqueous solution of citric acid as electrolytes. The electrical properties of the etched-foil capacitor were measured using a sulfuric acid solution as the top contact. The high surface area electrodes yielded very high capacitance densities of 35–40 μF/cm2.

Leakage current suppression in solution-deposited barium titanate films on copper foils

Abstract: Processing of high-permittivity ceramic films on free-standing bare copper foil for subsequent organic package integration requires high-temperature crystallization at low oxygen pressures. This frequently can result in incorporation of oxygen vacancies and copper diffusion into the film that enhances leakage current and degrade the reliability characteristics. Leakage current, breakdown voltage and electrical reliability of the devices were improved by incorporating 1% excess barium and manganese dopant. Incorporation of dopants also resulted in enhanced densification and grain refinement. Leakage current analysis indicated Space-Charge-Limited Conduction as the dominant conduction mechanism in both undoped and doped films. The mechanisms by which acceptor dopants suppress oxygen vacancy creation and migration are discussed. Capacitance densities of 1.5–3 μF/cm2, with breakdown voltages above 10 V, were demonstrated for 250–500 nm thin barium titanate films.

Extraction of electrical properties of nanomagnetic materials through meander-shaped inductor and inverted-F antenna structures

Abstract: This paper presents processing, integration and characterization of a new class of magneto-dielectrics consisting of metal nanoparticles in a polymer matrix for antenna applications. These nanomagnetic materials exhibit several attractive features for antenna applications, such as simpler thick-film processing, higher permittivity and permeability, and lower loss. Extraction of permeability and loss for such materials is usually cumbersome because both the permittivity and permeability are unknown. The meander-shaped inductor structures developed and reported here allow simpler fabrication and characterization of permeability and magnetic loss. Inverted-F antenna structures were designed, fabricated and tested to verify this method.

Novel Chip-Last Method for Embedded Actives in Organic Packaging Substrates

Abstract: Embedded actives are to bury thinned active chips into package substrates, as opposed to surface mounted devices (SMDs), which can achieve smaller form factor, better electrical performance and higher functionality than the SMD technology. While many embedded actives have been explored so far, they are based on chip-first and -middle approaches, in which the active chips are embedded before and during the build-up processes of package substrates, respectively. The most concern with those two current approaches is the loss accumulation associated with the build-up layer processes carried out right on top of the embedded chips, which is highly likely to lose the embedded chips during their packaging process. The reworkability to replace the faulty chips embedded with good ones and thermal management of the embedded chips are also issues since the embedded chips are totally surrounded by hard-cured polymers. In this paper, chip-last embedded active has been proposed to address some of the issues that are reported in current chip-first and -middle approaches, in which chips are embedded after all the package substrate processes including the build-up layers are completed, just like conventional SMD packaging. In the chip-last approach, a cavity is introduced within the build-up layers of package substrate and a chip is directly embedded into the cavity. A first proto-type of the chip-last embedded active will be demonstrated by developing various cavity formation processes within the build-up layers and then embedding 100 μm thick chips into the defined cavities.

Chip-last fan-out package with embedded power ICs in ultra-thin laminates

Abstract: The demand for ultra-miniaturized mobile electronics systems has placed stringent requirements on the form-factor, especially thickness, of electronic modules. A novel technology to enable embedding in 1 or 2 metal layer substrates using chip-last technology was introduced previously [1]. This paper focuses on first ever demonstration of chip-last embedding of functional dies in 1–2 metal layer thin core substrates, to achieve form factor and performance comparable to wafer level fan-out with improved yield, cycle time reduction, cost, testability and thermal management. Ultra-slim modules were obtained as a result of embedding thin-chips within the core instead of the build-up layers reported previously [2]. Performance of chip-last embedded actives has been successfully demonstrated previously [3] using low power RF ICs. Embedding power management ICs (PMIC), however, not only challenges high power dissipation capabilities of chip-last fan-out package but also its high current carrying capability, with many I/Os drawing ∼1A current. Since the embedded PMIC is rated at 2.3W dissipation, finite element modeling (FEM) was carried out to simulate thermal performance of the package under steady state conditions. Assuming uniform distribution of the 2.3W over the entire PMIC, FEM simulations depicted a maximum temperature of ∼52°C on the top of the embedded IC, a rise of ∼27°C from the base temperature of 25°C, indicating the heat dissipation to be a non-issue. Module substrates were built using 100μm BT as core and ABF as the cavity layer dielectric. Thinned functional ICs were assembled in the laser-ablated cavities using previously demonstrated Cu-Cu thermo-compression bonding [4, 5]. The resulting module thickness with the embedded IC was ∼200μm, a reduction of more than 55% from the incumbent. The demonstrated ultra-thin laminate based fan-out package with embedded PMIC uses a simple fabrication process flow making it a manufacturing-friendly and cost effective solution. Therefore, the low layer count chip-last embedding technology has the potential to achieve ultra-miniaturization for future embedded sub-systems and systems.

Low cost system-in-package module using next generation low loss organic material

Abstract: Miniaturization of wireless sub-systems through high-density integration of actives and passives is in hour of need with the increasing demand for portable devices. Considering that a thin, planar form-factor is much sought-after for mobile devices, it is essential to shrink packages in terms of thickness. This paper presents, for the first time, super-thin, three-metal-layer WLAN LNA and receiver modules with chip-last embedding pioneered by Georgia Tech Packaging Research Center (GT-PRC). The modules composed of a thin organic core and an organic build up layer measure 130 um in thickness, which is smaller by a factor of nearly 10× compared to the conventional wire-bonding or flip-chip packages. Such miniaturization was primarily achieved by shrinking of embedded passives with the use of next generation material X-L (high Dk) with high dielectric constant. The modules were fabricated using conventional low cost process with the addition of cavity fabrication through laser ablation, followed by embedding of 100 um-thick GaAs dies. The receiver module was measured to have a gain of 9.2 dB at 2.4 GHz, and out-of-band rejection of nearly 30 dB at 2 GHz and 5 GHz.

Modeling and design of an ultra-miniaturized WLAN sub-system with chip-last embedded PA and digital dies

Abstract: System integration by die-embedding within electronic packages offers significant advantages in miniaturization, cost and performance for mobile devices. This paper presents the functional design and analysis of ultra-thin packages that combine embedded actives (GaAs Power Amplifier and a baseband digital IC) with embedded passives (band-pass filters), leading to an ultra-miniaturized WLAN sub-system. This chip-last design routes embedded dies in the outer build-up layer, using Embedded MEMS Actives and Passives (EMAP) technology being developed in the Georgia Tech PRC's industry consortium, as an alternative, lower cost approach over current chip-first and chip-middle methods. Electromagnetic (EM) simulations were performed in order to tune the electrical performance of interconnections based on die specifications and package configuration. The digital package was designed with multiple power-ground pair islands to enhance noise isolation, while improving overall signal and power integrity. The embedded module designs for RF transmitter and the baseband IC measure at 2.8mm × 3.2mm × 0.25mm and 10mm × 10mm × 0.25mm respectively, achieving over 4.5× volume reduction compared to existing wire-bond packages.

Integration of precision resistors and capacitors with near-zero temperature coefficients in silicon and organic packages

Abstract: This paper reports novel material and process technologies for near-zero Temperature-Coefficient Resistors (TCR) and zero temperature coefficient of capacitance (TCC) capacitors and their integration into organic or silicon packages for precision RF components. A new concept of self-compensating resistors, leading to zero TCR was explored and demonstrated for the first time, using heterogeneous resistor stack structures consisting of metal layers with positive TCR and semiconducting oxide layers with negative TCR. Zero TCC capacitors were demonstrated with a film-stack consisting of ceramic nanocomposites of positive TCC and negative TCC. In both cases, the film thickness was designed such that there is internal compensation in temperature deviation, which results in zero temperature-coefficient. Material models were developed for the film-stack to design the films for zero temperature-coefficient.

Improvement of Plated Copper Adhesion in Glass Interposer Applications

Abstract: Glass interposers offer a compelling alternative to silicon interposers with highest I/Os and excellent electrical performance, with potential for low cost from large panel processing. For sub-32nm IC nodes and 3D-IC packages at fine I/O pitch, organic substrates are reaching their limits in terms of I/Os, design rules and CTE mismatch. Glass offers the best combination of electrical insulation, dimensional stability, CTE match to Si ICs, and flat, smooth surfaces for ultra-fine line lithography. The biggest challenge in glass interposers is the formation and metallization of ultra-fine pitch through vias. The formation of small via diameters in thin glass substrate have been demonstrated. The focus of this paper will be on wet metallization of glass interposer with through via, and addressing the challenge of providing reliable adhesion on the copper-to-glass interface. Two main approaches are currently pursued in the wet-chemical metallization of glass interposers: the electroless and electrolytic coppe...

Suppression of Vertical Electromagnetic Coupling in Multilayer Packages

Abstract: This paper proposes an effective approach to suppress vertical electromagnetic (EM) coupling in multilayer packages operating at GHz frequencies. In the case of packages with embedded actives where there are large apertures (die sized) in the metal planes and cavities in dielectric layers to accommodate the chips, the effect of EM field coupling is significant. The method involves EM band-gap structures for suppressing vertical coupling and the isolation band can be tuned over different frequency ranges. In addition, this paper puts forth a methodology for predicting the frequency range of the isolation band achieved by the coupling suppression technique. The proposed methodology is demonstrated through simulations and measurements.

Verbindungsanordnungen und Verfahren zum Herstellen und Verwenden derselben

Abstract: Die verschiedenen Ausfuhrungsformen der vorliegenden Erfindung sehen Chip/Substrat-Verbindungsanordnungen mit feinem Abstand sowie Verfahren zum Herstellen und Verwenden der Anordnungen vor. Die Anordnungen umfassen im Allgemeinen einen Halbleiter mit einem Die-Pad und einem Bump, der darauf angeordnet ist, und ein Substrat mit einem darauf angeordneten Substratpad. Der Bump ist so konfiguriert, dass er mindestens einen Teil des Halbleiters mit mindestens einem Teil des Substrats elektrisch verbindet, wenn der Bump mit dem Substratpad kontaktiert wird. Wenn ferner der Bump mit dem Substratpad kontaktiert wird, werden mindestens ein Teil des Bumps und mindestens ein Teil des Substratpads verformt, um dazwischen eine nichtmetallurgische Verbindung zu erzeugen.