Showing papers by "Rao Tummala published in 2014"

Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon

Abstract: A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs. The 3-D IC stacking approach to achieve high bandwidth has several drawbacks, including the need for TSVs through the logic die, thermal management within the 3-D stack, and the high manufacturing cost associated with wafer-based TSV processing. This paper presents design, fabrication, and electrical characterization of small TPVs (15–40 $\mu{\rm m}$ in diameter) in 30- $\mu{\rm m}$ thin glass to achieve an ultrathin 3-D interposer. This paper also reports the first demonstration of ultrasmall TPVs in glass (15 $\mu{\rm m}$ ) with same dimensions as TSVs in silicon. The signal insertion loss and crosstalk behavior of TPVs in ultrathin glass were investigated and found to be superior to TSVs using 3-D electromagnetic simulations. In demonstrating the 3-D interposers, two process-related challenges were addressed in this paper, namely: 1) defect-free formation of ultrasmall TPV holes with diameters of 15 $\mu{\rm m}$ at 27- $\mu{\rm m}$ pitch and 2) TPV metallization with copper. The fabricated TPVs in ultrathin glass showed a good model to hardware correlation of signal transmission with insertion loss ${ at 20 GHz. The results in this paper suggest that the 3-D interposer concept can be a simpler alternative to 3-D IC stacking with TSVs to achieve high bandwidth between the logic and memory devices.

Demonstration of 3–5 μm RDL line lithography on panel-based glass interposers

Abstract: Interposer technology is becoming important to interconnect ultra-high performance ICs with ultra-high density I/Os. Silicon interposers fabricated by back-end of line (BEOL) wafer processes address these wiring density requirements, but are limited by their high cost and by their high electrical losses. Organic interposers have limitations too. Their limitations are due to their poor dimensional stability, which require larger capture pads, which limit the I/O density Glass has been proposed by Georgia Tech [1-4] as a superior interposer material to address the limitations of both silicon and organic interposers in recent years. This paper describes the first demonstration of low cost and double sided glass interposer with 3-5 μm line lithography to form multilayer redistribution layers (RDL) to achieve 20 micron bump pitch, ready for chip-level copper interconnections. Unlike prior work using wafer based RDL processes or thin film wiring applied to organic cores, this research applies low cost laminate-like processes, scalable to large panels for lowest cost. To achieve this, semi-additive plating (SAP) process, combined with high resolution dry film photoresists, was optimized to fabricate fine-pitch copper traces with 3-5 μm lines on thin polymer films, laminated on thin glass. Such an ultra-high I/O density of interconnections form the backbone of 2.5D interposers, interconnecting multiple chips. Such ultra-small pitch copper traces can reduce the number of wiring layers required, thus reducing the cost. Compared to sub-micron Cu traces on Si interposers, these 3-5 μm lines are lower in resistance.

Modeling, design, fabrication and characterization of first large 2.5D glass interposer as a superior alternative to silicon and organic interposers at 50 micron bump pitch

Abstract: This paper describes the first design and fabrication of a large 25D glass interposer with 50 µm pitch chip-level interconnections made of 6 layers of 3 µm re-distribution (RDL) wiring Many applications including high-performance networking and cloud computing data centers require ultra- high-bandwidth of the magnitude of 512 GB/s Silicon-based 25D interposers are the only approaches being pursued by the industry to meet this need, enabled by sub-micron BEOL wiring in the wafer fabs Such interposers, however, are too expensive for most applications Glass interposers are superior to silicon interposers due to their high dimensional stability, low loss tangent, and large panel processing ultimately leading to lower cost This paper presents the design, fabrication and electrical characterization, leading to the first fabrication of 25D glass interposers with 50 µm I/O pitch with 3 µm lines Double-sided panel processing utilizing thin, low-loss dryfilm polymer dielectrics and SAP copper plating, with differential spray etching techniques, was used to fabricate 3 m wide transmission lines on 25mm x 30mm glass interposers processed on a 300 m thick 150mm x 150mm glass panels A six-metal layer test vehicle with two daisy chain, 10mm x 10mm test chips at 100 µm spacing, was fabricated and assembled by thermo-compression bonding of Cu microbumps and SnAg solder caps Ultra-fine 3 µm escape routing was demonstrated on a two-metal layer test vehicle High frequency characterization of 3 µm lines showed low loss of 012 dB/mm at 2 GHz

Modeling, Fabrication, and Characterization of Low-Cost and High-Performance Polycrystalline Panel-Based Silicon Interposer With Through Vias and Redistribution Layers

Abstract: Interconnections between integrated circuits and print circuit boards are primarily achieved currently with organic packages at high I/O pitch. Organic packages, however, are limited by poor thermal and dimension stabilities for them to act as fine pitch interposers. To address these challenges, silicon interposers are being developed. Current silicon interposers, based on through-silicon via (TSV) techniques, suffer from high production cost, because of expensive CMOS-grade silicon, expensive TSV process and smaller wafer sizes. They also suffer from high electrical loss in spite of thin SiO 2 interfacial layers. This paper, for the first time, demonstrates a lower cost and higher performance silicon interposer. It is based on panel-based polycrystalline silicon with through-package vias (TPVs) and redistribution layers, and a simple and double-side process with thick polymer liner inside the TPV. Electrical modeling was carried out that shows the better electrical performance of polycrystalline silicon interposer compared with traditional single-crystalline silicon interposer. The polycrystalline silicon interposer test vehicles with up to four metal layers were demonstrated and characterized. The measurement results showed good electrical performance and matched well with the simulations.

Glass-polymer optical interposer

Abstract: An optical interposer that includes a glass substrate (102) having one or more optical vias (104) extending through the glass substrate. A first optical polymer (112) may be bonded to the substrate and to interior surfaces of the one or more optical vias. Implementations include one or more optical via cores comprising a second optical polymer (110) that has a greater refractive index than the first optical polymer. The one or more optical via cores may be at least partially surrounded by the first optical polymer. Embodiments include encapsulated optical waveguides in communication with the optical vias and/or via cores. Example implementations include layers of electrical insulation (114), electrical traces, and electrical vias (118). A method of manufacture includes forming the optical vias by laser ablation. Certain embodiments may include chemically etching the inside of the vias to improve surface roughness.

First demonstration of reliable copper-plated 30μm diameter through-package-vias in ultra-thin bare glass interposers

Abstract: This paper reports the first demonstration of the reliability of through package copper vias (TPV) with 30 μm diameter at 120 μm pitch in ultra-thin 100 μm thick glass to achieve high-density vertical interconnections in 2.5D and 3D interposers and packages. Bare glass with 100 μm thickness was used to demonstrate the via formation, metallization and reliability of small through-package-vias. The reliability concerns at this fine pitch were addressed through modeling and design from first principles, followed by experimental validation with test-vehicle fabrication and reliability characterization. Thermo mechanical reliability of TPV was analyzed through finite element modeling to estimate stresses inside TPV during thermal cycling and provide design guidelines. For experimental validation, test samples with daisy chains of glass TPVs were fabricated and subjected to accelerated thermal cycling tests between -55°C and 125°C to assess the thermomechanical reliability. Resistance of each daisy chain was measured periodically as a method to detect failure initiation. Majority of the TPV chains passed the reliability test without significant change in resistance. TPV daisy chains that showed changes in resistance were cross-sectioned and failure analysis indicated that the early failures of TPV in glass were related to process defects coming from via-hole formation and metallization.

Flip-chip on glass (FCOG) package for low warpage

Abstract: As microelectronic industry moves toward stacking of dies to achieve greater performance in smaller footprint, there are several reliability concerns when assembling the stacked dies on current organic substrates. These concerns include excessive warpage, interconnect cracking, die cracking, and others. Silicon interposers are being developed to assemble the stacked dies, and then to assemble the silicon interposers onto organic substrates. Although such an approach could address stacked-die to interposer reliability concerns, there are still reliability concerns between the silicon interposer and the organic substrate. The ongoing work at the Packaging Research Center is exploring the use of glass substrates as a superior alternative to organics in I/Os and to silicon in electrical performance. In addition, glass provides intermediate and tunable coefficient of thermal expansion between silicon and organic, good mechanical rigidity, large-area panel processing for low cost, planarity, and better electrical properties. However, glass is brittle and low in thermal conductivity, and there is very little work in existing literature to examine glass as a potential substrate material. In this paper, we examine large glass panels as substrates for microelectronic packages through experiments and simulation. Starting with a 150 × 150 mm glass panel with a thickness in the range of 100 to 300 um μm, we have built alternating layers of dielectric and copper on both sides of the panel. The panels go through typical cleanroom processes such as lithography, electroplating, etc. Upon fabrication, the panels are diced into individual substrates of 25 × 25 mm, and a 10 mm × 10 mm Si die with a peripheral staggered bump pitch of 80/40 um μm is then assembled on the glass substrate by thermocompression bonding with a pre-applied no-flow underfill. The warpage of the flip-chip assembly is measured. In parallel to the experiments, numerical models have been developed. These models account for temperature-dependent properties of the dielectric as well as viscoplastic behavior of the solder. The models also mimic material addition and etching through element “birth-and-death” approach. The warpage from the models has been compared against experimental measurements for glass substrates with flip-chip assembly. It is seen that the glass substrates provide significantly lower warpage compared to organic substrates, and thus could be a potential candidate for future 3D and 2.5D systems.

Cobalt–Polymer Nanocomposite Dielectrics for Miniaturized Antennas

Abstract: Cobalt–polymer magnetic nanocomposites have been synthesized and characterized for their microstructure and properties such as permeability, permittivity, dielectric and magnetic losses from 100 MHz to 2 GHz to study their suitability as antenna dielectrics. Oxide-passivated cobalt nanoparticles were dispersed in epoxies to form nanocomposite toroids and thin-film resonator structures on organic substrates. Permeabilities of 2.10 and 2.65 were measured up to 500 MHz, respectively, with 25-nm to 50-nm and 5-nm nanoparticles in the nanocomposites. The loss tangent ranged from 0.02 to 0.04 at these frequencies. A combination of stable permeability of ∼2 at 1 GHz to 2 GHz and permittivity of ∼7 was achieved with nanocomposites having 5-nm nanoparticles. The magnetic nanomaterials described in this paper can overcome the limitations from domain-wall and eddy-current losses in microscale metal–polymer composites, leading to enhanced frequency stability. The paper also demonstrates integration of metal–polymer nanocomposites as thin-film build-up layers with two-metal-layer structures on organic substrates.

Tunable and Miniaturized RF Components with Nanocomposite and Nanolayered Dielectrics

Abstract: du Abstract- Nanocomposite and nanolayered dielectrics provide new avenues to enhance the performance of RF and power components. They enable engineering of properties such as permeability, permittivity, frequency­ and temperature-stab ility, and tunability, along with low loss, to miniaturize next-generation multiband RF modules that require higher functional density and improved performance. This paper demonstrates two such advances in nanodielectrics: l.)Magnetic nanocomposites for miniaturization of antennas, meta materials and other RF components, 2.)Nanolayered stack dielectrics for tunable RF components with temperature- and frequency-stabilit y and low loss. The materials design, synthesis, processing and characterization to demonstrate the superior properties are presented.

Analysis of Power Distribution Network in glass, silicon interposer and PCB

Abstract: D integration using a glass interposer and through glass via technologies is expected to improve the performance of a whole system significantly. However, due to the high quality factor of the glass substrate, the sharp impedance peaks on the Power Distribution Networks arise at the resonances. When the mode resonances occur, performance of a whole system could be degraded. Segmentation based impedance- estimation was used to analyze the PDN impedance and analyzed system degradation at resonance frequencies. To maximize advantages of the glass interposers, the PDN should be carefully designed to suppress the resonances. Considering the current status of the glass fabrication processes, we propose that placing the ground vias near the signal vias is the most promising solution for maximizing the advantages of the glass interposers.

High-frequency characterization of through package vias formed by focused electrical-discharge in thin glass interposers

Abstract: This paper presents the modeling, design, fabrication and characterization, up to 30 GHz, of low loss and high aspect-ratio 55 μm diameter through package vias (TPVs) in 300 μm thick glass interposers. These TPVs were fabricated using a novel, high-throughput, focused electrical discharge method and low cost panel-based double-side metallization processes. Such a glass interposer is targeted at two emerging applications, (a) large 30 mm to 60 mm body size 2.5D interposers to achieve 28.8 Gbps logic-memory bandwidth and (b) 3D interposers for mm wave applications at 28 GHz local multipoint distribution service (LMDS) for future 5G networks. Accurate measurement of the electrical performance of fine pitch metallized through vias in glass up to 30 GHz and beyond is critical for both these high performance interposer applications. In this paper, two novel characterization methods are applied: 1) the short-circuit-and-open-circuit method and 2) the dual-via-chain method. The resistance and the inductance of a single via are extracted by using a short-circuit structure along with an open-circuit structure. At 10 GHz, the values for the series resistance and inductance have average values of 0.1 Ω and 160 pH respectively. Long dual-via chains were designed to evaluate their performance in insertion loss, delay and eye diagram. The insertion loss achieved with the longest dual-via chain was found to be less than 1 dB/cm up to 30 GHz with only a 6.2 ps delay in the TPVs, and the simulations indicate a wide open eye.

Adhesion and reliability of direct Cu metallization of through-package vias in glass interposers

Abstract: Direct metallization of bare glass with copper is required to reach the full potential low-cost benefit of glass interposers. However, this poses a fundamental materials challenge associated with copper-to-glass adhesion. Intermediate polymer liners on glass have been used by others, adding an extra material and processing step. In this paper, three approaches to direct metallization of copper to glass interposers are explored and reported. Electroless plating, sputtering followed by electrolytic plating, and sol-gel were investigated as Cu deposition methods with an emphasis on adhesion and reliability of copper to bare glass. The adhesion and reliability performance of films were characterized by tape-testing, peel-strength measurements, and thermal-shock testing. Based on these results, individual assessments are made for each approach and compared with others to assess future directions.

Large low-CTE glass package-to-PCB interconnections with solder strain-relief using polymer collars

Abstract: This paper reports the use of circumferential polymer collars as a strain-relief mechanism to improve the fatigue life of low-CTE package-to-PCB solder interconnections, while preserving SMT-compatibility and reworkability. Acting as a partial underfill, the polymer-collar serves to block shear deformation at the solder-package interface, and redistributes the load to reduce the overall plastic strain concentration in the solders. It also suppresses failure initiation from defective surface sites and, thus further enhances reliability. Ultra-thin glass 100μm interposers were fabricated in 18.4 mm × 18.4 mm size to model, design and demonstrate the reliability enhancement with the polymer-collar approach. The detailed interposer design and fabrication process with laminated dielectric and metallization layers on both sides is presented. A new class of epoxies with low modulus, without the incorporation of silica fillers, was used to act as the polymer collars. The polymer collars are formed by spin-coating with an optimized thickness to provide the best compromise between the effective strain relief and reworkability. Board-level assembly was performed using standard SMT processes for glass interposers with and without polymer collars. Thermal cycling reliability testing (-40°C to 125°C) of interposers, assembled on PCBs with and without polymer collars for various thicknesses of the collar was performed.

First demonstration of a surface mountable, ultra-thin glass BGA package for smart mobile logic devices

Abstract: This paper presents the first demonstration of an ultra-thin glass BGA package that is assembled on to mother board with standard SMT technology Such a package has many new advances that include ultra-thin glass, high speed through via hole formation and copper metallization, double-side RDL wiring with advanced 3 micron ground rules, and Cu-SnAg microbump assembly of a 10mm silicon test die Glass, as a package, overcomes the shortcomings of organic packages in bump pitch, CTE mismatch to Si and warpage and silicon interposers in electrical performance and cost Glass packages are being developed to manufacture both as wafers for improved performance over Si and as panels to improve bump pitch over organic packages Glass, therefore, is not just a high performance and low volume technology, like silicon interposers, but a pervasive package technology with lower cost, higher performance and thinner than silicon and organic packages Glass has compelling benefits in thickness and I/O pitch reduction and reliability for one of the highest volume applications, namely, the packaging of high I/O logic devices for smart mobile systems This paper represents a paradigm shift in ultra-thin packages using large glass panels for future smart mobile and high performance devices, and the first demonstration of 100um thin glass packages with 50-80um c hip-level I/O pitch and 18 mm × 18mm body size surface mount assembly at 400um pitch

Finite Element Analysis and Experiment Validation of Highly Reliable Silicon and Glass Interposers-to-Printed Wiring Board SMT Interconnections

Abstract: Interposers that support high input/output density are becoming critical for system miniaturization and high performance. Silicon and glass are emerging as the primary candidates for such high-density interposers, due to their outstanding dimensional stability, which enables layer-to-layer wiring with small vias. However, silicon and glass have very low coefficient of thermal expansion (CTE), 3–8 ${\rm ppm}/^{\circ}{\rm C}$ , compared with organic printed wiring board (PWB), which has a CTE of 12–18 ${\rm ppm}/^{\circ}{\rm C}$ . The large CTE mismatch between interposer and board raises reliability concern with the ball grid array interconnections. In this paper, compliant dielectric build-up layers laminated on silicon and glass interposers are explored as stress buffers to reduce the strain accumulated in solder interconnections. Finite element method was used to analyze the thermo-mechanical reliability of the interconnections, and predict the fatigue life of solder joints. Three types of low-CTE interposer materials were studied, low-CTE glass (3 ${\rm ppm}/^{\circ}{\rm C}$ ), high-CTE glass (8 ${\rm ppm}/^{\circ}{\rm C}$ ), and silicon (2.7 ${\rm ppm}/^{\circ}{\rm C}$ ). Test vehicles with the above three interposers at a size of 7.2 mm $\times\,$ 7.2 mm with 25- $\mu{\rm m}$ -thick polymer stress buffers laminated on both sides were fabricated, and assembled on organic FR-4 boards using Sn96.5Ag3Cu0.5 solder. The reliability of the solder interconnections, with the three different test vehicles, was studied using thermal cycling test from ${-}{40}^{\circ}{\rm C}$ to 125 $^{\circ}{\rm C}$ . The high-CTE glass sample was observed to survive 1800 thermal cycles before the first failure was detected in one of the corner joints. Experimental results of fatigue life of interconnections agreed well with finite element modeling results, and reliable interconnections between low-CTE interposer and organic PWB using stress buffers were demonstrated. Based on the validated model, parametric study was conducted to explore the influence of geometry and material properties of interposer on the thermo-mechanical reliability of the solder interconnections, as a guideline for interconnection design of similar interposers.

Experimental demonstration of the effect of copper TPVs (Through package vias) on thermal performance of glass interposers

Abstract: Glass has been proposed to be an ideal material for interposers to address the limits of both organic and silicon, except for its poor thermal conductivity compared to silicon. This paper proposes to use large number of copper through package vias (TPVs) that can be fabricated at low cost to improve this shortcoming. We report on experimental fabrication and evaluation of the effect of copper TPVs on thermal performance of glass interposer structures. Copper via arrays with different via densities (0.62 vias/mm 2 ~ 22 vias/mm 2 ) were fabricated in glass interposer structures by using low cost laser drilling and electroplating. The thermal performance of such structures was quantified by measuring spatial temperature distribution, including the maximum value around the heat source. This study provides fundamental understanding of heat transfer within thermally-enhanced glass interposers, and offers guidelines for the design of copper via arrays to improve their thermal properties.

Accelerated SLID bonding using thin multi-layer copper-solder stack for fine-pitch interconnections

Abstract: Emerging 2.5D and 3D package-integration technologies for mobile and high-performance applications are primarily limited by advances in ultra-short and fine-pitch off-chip interconnections. A range of technologies are being pursued to advance interconnections, most notably with direct Cu-Cu interconnections or Cu pillars with solder caps. While manufacturability is still a major concern for the Cu-Cu interconnections technologies, the copper-solder approaches face limitations due to solder-bridging at fine-pitch, electromigration, and reliability issues. Thus, novel low-temperature, low-pressure, high-throughput, cost-effective and manufacturable technologies are needed to enable interconnections with pitches finer than 15 microns. This paper focuses on an innovative multi-layered copper-solder stack approach to achieve fine-pitch off-chip interconnections with no residual solders after assembly. Interconnections using this new technology enable higher current-handling because of the stable intermetallics, high-throughput assembly, and high yield even at low stand-off heights. The elimination of solder-intermetallic (IMC) interfaces is also expected to enhance the joint strength. This paper describes the design, fabrication, assembly and characterization of such stacked copper-solder interconnections. A detailed study of the effect of bonding parameters such as temperature and time on the rate of formation of stable Cu-IMC-Cu structures is presented. Test-vehicles were designed and fabricated as the first demonstration of this technology.

A new era in manufacturable, low-temperature and ultra-fine pitch Cu interconnections and assembly without solders

Abstract: This paper presents the first demonstration of a high-throughput die-to-panel assembly technology to form Cu interconnections without solder at temperatures below 200°C. This interconnection technology, previously established with individual single-chip packages on both organic and glass substrates, at pitches down to 30μm, is brought up to a significant manufacturable level by two major innovations: 1) ultra-fast thermocompression bonding (TCB) process with pre-applied polymer, in air, and without any prior surface activation; 2) die-to-panel assembly process with heating from die side exclusively for reduced substrate warpage. The initial proof of concept reported in this paper consists of assembly of 15 silicon dies with Cu bumps at 100 μm pitch, on a 3” × 5” organic substrate, by sequential TCB at 210°C for 3 seconds, and 190°C for 10 seconds. X-ray analysis, C-SAM imaging, cross-section observation with optical microscopy and SEM, and electrical yield characterization indicate the formation of strong metallurgical interconnections. This pioneering technology addresses many manufacturability challenges presently hindering the technology-transfer of direct Cu-Cu bonding, the “holy grail” in the semiconductor industry, by offering a potentially low-cost, high-throughput solution, compatible with industry-standard assembly lines. Scalable to ultra-fine pitches onto low-CTE glass, silicon or organic packages, it has the potential to become a major enabler for the next two or more decades.

Nanomagnetic Thinfilms for Advanced Inductors and EMI Shields in Smart Systems

Abstract: Nanomagnetics provide unique opportunities to address the fundamental limitations of traditional electronic materials for miniaturization of RF and power components, while simultaneously enhancing their performance. This paper demonstrates nanomagnetic films and processes for power inductors and EMI shield applications. A DC-RF co-sputtering process was developed to synthesize cobalt-based nanogranular films with superior properties compared to microscale magnetic materials. The benefits of this material for miniaturized power inductors are demonstrated with analytical models. The second part of the paper demonstrates miniaturization of electromagnetic interference (EMI) shields with nanomagnetic film-stacks.

Coaxial through-package-vias (TPVs) for enhancing power integrity in 3D double-side glass interposers

Abstract: Double-sided 3D glass interposers and packages, with through package vias (TPV) at the same pitch as TSVs in Si, have been proposed to achieve high bandwidth between logic and memory with benefits in cost, process complexity, testability and thermal over 3D IC stacks with TSV. However, such a 3D interposer introduces power distribution network (PDN) challenges due to increased power delivery path length and plane resonances. This paper investigates the use of coaxial through-package-vias (TPVs) with high dielectric constant liners as an effective method to deliver clean power within a 3D glass package, and provides design and fabrication guidelines to achieve the PDN target impedance. The Coaxial TPV structure is simulated using electromagnetic (EM) solvers and a simplified equivalent circuit model to study via impedance and parasitics. Test vehicles with anodized tantalum oxide capacitors were fabricated in ultra-thin, 100μm thick glass interposers to demonstrate process feasibility, with a capacitance density of 5 nF/mm 2 . Self-impedance (Z11) of a 3D glass interposer containing the coaxial TPVs was analyzed with variations in (a) Via location, (b) Number of coaxial vias, and (c) Via capacitance and stack-up, to provide optimal PDN design guidelines. Based on the above parameters, the added decoupling vias achieved more than 30% impedance suppression over multiple resonance frequencies between 0.5-6 GHz, providing an effective and flexible PDN design method for double-side 3D glass interposers.

Double-Side Process and Reliability of Through-Silicon Vias for Passive Interposer Applications

Abstract: Through-silicon vias (TSVs) for passive interposer applications are being widely developed in industry and academia. This paper for the first time presents a double-side process to fabricate such TSVs. Such a process has many benefits, including not requiring carrier wafers for a wafer size between 150 and 200 mm and avoiding the chemical mechanical polishing processes after Cu plating. It thus significantly reduces the fabrication process steps compared with a traditional TSV. The reliability of TSVs formed this way has been studied by fabricating daisy chains and testing them for temperature cycling. Detailed mechanical failure mechanism analysis by a scanning electron microscope has been also carried out. In addition, finite-element models have been developed to analyze the fabrication-induced stresses and to estimate the thermomechanical reliability of the fabricated TSV structures.

Thin polymer dry-film dielectric material and a process for 10 um interlayer vias in high density organic and glass interposers

Abstract: This paper describes the first demonstration of 10 μm diameter interlayer vias in low-moisture uptake and low surface-roughness dry film polymer dielectric for multi-layered re-distribution layer (RDL) structures to achieve 50 μm bump pitch in high density organic and glass interposers. A new series of polymer dry films, ZS-100, at 10 μm thickness were deposited on thin and low CTE organic or glass cores using double-sided vacuum lamination processes. The ultra-small vias were fabricated by 248nm KrF excimer laser drilling, followed by electroless and electrolytic copper plating. Fully-filled via structures were successfully fabricated without any chemical-mechanical polishing. The processes demonstrated in this paper achieve much finer bump pitch than current organic packages, and can be scaled to large panels leading to lower cost than previous work in fine pitch Si interposers using back-end of line (BEOL) wafer processes.

Analysis and optimization of a power distribution network in 2.5D IC with glass interposer

Abstract: 2.5D integration based on interposer technologies provides high density integration and high system bandwidth. Among many materials for the interposer substrate, glass could be a promising material since it provides low signal loss and its ultra-thin thickness. When chips are stacked on the glass interposer, power distribution network impedance of 2.5D IC must be estimated, analyzed and optimized since it directly affects chips performance and signal integrity. In this paper, we modeled 2.5D-power distribution network using a segmentation method and verified with 3D-EM simulation. With verified model, power distribution network impedance of 2.5D IC with glass interposer was estimated and analyzed. Also modeled 2.5D-power distribution network was optimized with decoupling capacitors. Optimization was based on the target impedance derived from the current spectrum of switching I/O. Target impedance based on the current spectrum allowed more flexible power distribution network design compared to the conventional target impedance.

Ultraminiaturized WLAN RF Receiver Module in Thin Organic Substrate

Abstract: This paper presents the design, analysis, and demonstration of an ultra-thin wireless local area network (WLAN) RF receiver module with chip-last embedded actives and embedded passives in a low-loss organic substrate using system-on-package approach. The overall thickness of the module, including the embedded dies, is 160 μm- more than 3× thickness reduction compared to current wire-bond and flip-chip packages. The receiver module consists of gallium arsenide low-noise amplifier (LNA) dies, chip-last embedded in an ultrathin, low-loss organic substrate, and connected to a substrate-embedded three-metal-layer band-pass filter (BPF) in close proximity. Full-wave electromagnetic simulation was performed on a 3-D model of the designed receiver module to obtain its two-port scattering parameters (S-parameters) and to study noise coupling between the power-supply network and the signal path. The receiver module was then fabricated, tested for yield of the BPF, assembled and characterized, and the measured results were correlated with simulation. The BPF dimensions in the package were 1.5 mm × 2.9 mm × 0.15 mm, and its measured pass-band insertion loss was 2.3 dB with more than 15 dB return loss. The receiver module (LNA + BPF) dimensions were 5.5 mm ×2 mm ×0.16 mm, and it had a measured peak gain of 11 dB with more than 30 dB attenuation in the adjacent-band, indicating excellent performance in a miniaturized form-factor.

Design and demonstration of large 2.5D glass interposer for high bandwidth applications

Abstract: In this paper, a large 2.5D glass interposer is demonstrated with 50 um chip-level interconnect (FLI), 3/3 um line and space (L/S) escape routing, and six metal layers, which are targeted for JEDEC high bandwidth memory (HBM). Our routing design suggests that double sided panel processing with 3/3 um L/S can accommodate required signal lines for HBM. Then, 3/3 um L/S transmission lines on 25mm × 30mm glass interposers with 300 um core thickness can be realized by utilizing semi additive process. Finally, 10mm × 10m dies with daisy chains can be successfully bonded to 25mm × 30mm glass interposer with 6 metal lines using copper microbumps with SnAg solder caps.

Magneto-dielectric material characterization and antenna design for RF applications

Abstract: Antenna miniaturization without deteriorating performance is challenging because the performance is bounded by fundamental limits depending on the size of the antenna Magneto-dielectric materials, however, have been reported as providing new possibilities for antenna miniaturization in many recent studies In this paper, a novel material characterization method which is a cavity perturbation technique (CPT) with substrate integrated waveguide (SIW) cavity resonator is presented for extracting the properties of magneto-dielectric material CPT formulas for extracting complex permittivity and complex permeability are explained and modification process using 3D EM simulation tool is discussed Design and fabrication of SIW cavity resonators is presented The frequency dependent properties of permittivity and permeability for synthesized magneto-dielectric material are extracted in the frequency range of 1-4 GHz Microstrip patch antenna working at 1GHz on magneto-dielectric substrate has been designed and simulated in this paper

Modeling, design, and demonstration of ultra-miniaturized and high efficiency 3D glass photonic modules

Abstract: This paper presents the modeling, design, and demonstration of an ultra-miniaturized 2.5D optical transceiver module using ultra-thin glass interposers with electrical and optical through vias. The 3D Glass Photonics (3DGP) technology with double sided attach of electrical and photonics ICs can achieve ultra-high bandwidth with improved power efficiency at lower cost than other photonic integration such as silicon photonics and organic boards. Thin glass substrates with 60um diameter through vias were fabricated with copper plated electrical vias and polymer-filled optical vias, formed simultaneously. Re-distribution layers were fabricated on top of these integrated vias for electrical interconnections. The 2.5D optical module produced this way features flip-chip bonded VCSEL and driver chips. Initial measurements of the optical vias showed 1.2 dB of loss.

Modeling, design and demonstration of multi-die embedded WLAN RF front-end module with ultra-miniaturized and high-performance passives

Abstract: This paper demonstrates, for the first time, a Wireless Local Area Network (WLAN) radio frequency (RF) front end module (FEM), incorporating the smallest, high-performance band-pass filter (BPF) on a 110μm-thin organic substrate with chip-last embedded actives and thin-film passives. The FEM consists of a power amplifier (PA) die, a switch die, and two low-noise amplifier (LNA) dies, integrated with a BPF and a low-pass filter (LPF). Full-wave electromagnetic (EM) simulations are employed to study the signal path loss, EM radiation and coupling. The BPF and LPF have 0.25dB and 0.5dB insertion loss respectively, with in-substrate dimensions of 1mm x 1mm x 0.05mm. The PA die shows a gain of around 10.8 dB at 2.4GHz. The path between the antenna and the amplifiers is also characterized to have a loss of 3dB. The electromagnetic coupling from the PA output to the LNA input and to the PA power supply is simulated using full wave EM solver HFSS and found to be higher than 60dB, indicating very good EM isolation. Each block of the FEM is individually characterized and combined using Agilent ADS to obtain the complete S-parameter performance. Both the transmitter and receiver chains have gain of 9dB.

Magneto-dielectric characterization and antenna design

Abstract: Antenna size has fundamental limits based on the frequency of operation and performance required. In the past, various methods have been developed to miniaturize antennas with limited success. Magneto-dielectric materials, however, have been reported as providing new opportunities for effective antenna size reduction in many recent studies. In this paper, a novel material characterization method which is a cavity perturbation technique (CPT) with substrate integrated waveguide (SIW) cavity resonator is presented for measuring electric and magnetic properties of magneto-dielectric material. CPT formulas for extracting complex permittivity and complex permeability are explained and modification process using 3D EM simulation tool is discussed. Design and fabrication of SIW cavity resonators is presented. The frequency dependent properties of permittivity and permeability for synthesized magneto-dielectric material are extracted in the frequency range of 1-4 GHz. Planar inverted F antenna (PIFA) working at 1GHz on magneto-dielectric substrate has been designed and simulated in this paper.

Insulation reliability of fine-pitch through-vias in glass fiber reinforced halogen-free epoxy substrates

Abstract: Insulation failures from electrochemical migration is a major reliability concern for achieving reliable small conductor spacings in glass fiber reinforced substrates in the presence of humidity and DC bias voltage. In this study, insulation reliability of fine-pitch copper plated-through-vias in two different halogen-free epoxy substrates was investigated using accelerated testing condition (85 °C, 85 % RH and 100 V DC). The test vehicles included two different conductor geometry: (1) through-via to through-via (spacing: 100 and 150 μm) and (2) through-via to surface-trace (spacing: 75 μm). In accelerated testing, the through-via to through-via test vehicles exhibited insulation failures (failure criterion: 1 MΩ) with a strong dependence on via spacing with through-via spacing of 100 μm showing significantly shorter time to failures compared to test vehicles with spacing of 150 μm. Failure analysis revealed cracking in resin-glass fiber interfaces and within the resin matrix between the failed through-vias. The through-via to surface-trace test vehicles, on the other hand, did not exhibit failures based on the 1 MΩ criterion. However, occurrence of electrochemical migration was visible after optical inspection of the test vehicles. Elemental characterization revealed the presence of copper and chlorine in the resin-glass fiber interface, similar to the previously reported chloride-containing conductive anodic filament compound in printed wiring boards. Accelerating testing and failure analysis in this study indicates a strong dependence of insulation reliability on conductor spacing, geometry and substrate material properties.