Showing papers by "Rao Tummala published in 2017"

First Demonstration of 28 GHz and 39 GHz Transmission Lines and Antennas on Glass Substrates for 5G Modules

Abstract: High-performance and ultra-miniaturized mm-wave building block structures were demonstrated on panel-scale processed 3D glass packages for high-speed 5G communication standards at 28 and 39 GHz bands. To demonstrate the benefits of glass for 5G communications, various topologies of microstrip-fed patch antennas for different resonant frequencies and compact conductor-backed co-planar waveguides were modeled and designed for high bandwidth and efficiency in the mm-wave bands. The simulation results for insertion loss, antenna gain, and bandwidth are consistent with the measured values on the glass substrates. The fabricated conductor-backed coplanar waveguides show insertion losses of 0.2 –0.3 dB/mm with a channel length of 1.86 mm, and the fabricated antennas have more than around 6% bandwidth in the frequency range of 35 to 39 GHz.

Design and Demonstration of a 2.5-D Glass Interposer BGA Package for High Bandwidth and Low Cost

Abstract: Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass interposer described in this paper is superior to silicon interposer in cost and electrical performance, and to organic interposer in interconnect density. This paper describes a 2.5-D glass interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF.

Board-Level Thermal Cycling and Drop-Test Reliability of Large, Ultrathin Glass BGA Packages for Smart Mobile Applications

Abstract: Glass substrates are emerging as a key alternative to silicon and conventional organic substrates for high-density and high-performance systems due to their outstanding dimensional stability, enabling sub-5- $\mu \text{m}$ lithographic design rules, excellent electrical performance, and unique mechanical properties, key in achieving board-level reliability at body sizes larger than $15\times15$ mm2. This paper describes the first demonstration of the board-level reliability of such large, ultrathin glass ball grid array (BGA) packages directly mounted onto a system board, considering both their thermal cycling and drop-test performances. To investigate board-level reliability, glass BGA packages, $18.5\times18.5$ mm2 in body size and 100 $\mu \text{m}$ in thickness, were first designed and fabricated with a daisy-chain pattern. The glass test vehicles were fabricated at panel level, and then BGA balled by ball drop process with SAC105 solder balls, 250 $\mu \text{m}$ in diameter at 400- $\mu \text{m}$ pitch. After singulation, the glass packages were mounted onto printed circuit boards using standard surface mount technology assembly processes, and then subjected to reliability testing through thermal cycling and drop tests following JEDEC reliability standards. The effect of the coefficient of thermal expansion (CTE) of glass was evaluated by investigating low- and high-CTE glass substrates, with the CTEs of 3.8 and 9.8 ppm/°C, respectively. While all glass packages passed 1000 thermal cycles at −40/125 °C as predicted by thermomechanical modeling using the Engelmaier–Wild model, the fatigue life of high-CTE samples exceeded 5000 thermal cycles. In addition, 28/30 drop-test samples passed the required 40 and 200 drops on corner and inner circuits, respectively, with no clear effect of the glass CTE. The predominant failure modes were systematically identified for both reliability tests.

Miniaturized Bandpass Filters as Ultrathin 3-D IPDs and Embedded Thinfilms in 3-D Glass Modules

Abstract: This paper presents the modeling, design, fabrication, and characterization of an innovative and miniaturized thin-film bandpass filter with coupled spiral structures in ultrathin glass substrates (30– $100~\mu \text{m}$ ). This filter is demonstrated for two applications: 3-D integrated passive devices and embedded thinfilm filters in RF modules. A compact filter design was achieved through an integrated resonant structure that effectively utilizes the inductive and capacitive coupling between metal layers on either side of an ultrathin glass substrate or organic build-up layer. The designed filters (layout area $150~\mu \text{m}$ device thickness) were fabricated on a 30- $\mu \text{m}$ -thin glass substrate using a panel-based low-cost approach with double-side thin-film wiring processes. The effect of process variations on the performance of the proposed structures was also studied. Furthermore, an improved WLAN filter is designed and demonstrated by employing specific structural modifications. The measured frequency response of the filters shows good model-to-hardware correlation, with very low insertion loss (0.6 dB) in the passband, and high adjacent-band rejection (>25 dB).

First Demonstration of Panel Glass Fan-Out (GFO) Packages for High I/O Density and High Frequency Multi-chip Integration

Abstract: Ultra-thin, panel-level glass fan-out packages (GFO) were demonstrated for next-generation fan-out packaging with high-density high-performance digital, analog, power, RF and mm-wave applications. The key advances with GFO include: 1) large area panel-scalable glass substrate processes with lower cost, 2) silicon-like RDL on large panels with 1-2 µm critical dimensions (CD), 3) lower interconnect loss and 4) improved board-level reliability enabled by the tailorability of the CTE of the glass panels and compliant interconnections. Daisy-chain test dies were used to emulate an embedded device with the size of 6.469 mm × 5.902 mm, thickness of 75 µm and pad pitch of 65 µm. Glass panels with 70 µm thickness and through-glass cavities were first fabricated, and then bonded onto a 50 µm thick glass panel carrier using adhesives. After glass-to-glass bonding, the test dies were assembled into the glass cavities using a high-speed placement tool. RDL polymers were then laminated onto both sides and cured to minimize the warpage of the ultra-thin package. A surface planar tool was then used to planarize the surface of the panel to expose the copper microbumps on the die, followed by a standard semi-additive process (SAP) for the fan-out RDL layer. The shift and warpage of the die were characterized during the multiple process steps. Initial modeling and measured results indicate the potential for less than 5 µm die shift and less than 10-15 µm warpage across a 300 mm × 300 mm panel size.

Nanostructured miniaturized artificial magnetic conductors (AMC) for high-performance antennas in 5G, IoT, and smart skin applications

Abstract: The emergence of fan-out packaging for 5G and IoT applications has brought escalating performance concerns that arise from the proximity of radiating components such as antennas to lossy materials such as metals and silicon. These concerns also arise in wearable (“smart skin”) electronics where the human tissues act as the lossy substrate. Artificial magnetic conductors (AMC) are widely explored for enhancing the performance of antennas that are in close proximity to metallic surfaces and other lossy substrates such as silicon and human tissue. High-permittivity or high-permeability materials can be used to significantly reduce the sizes of AMCs. Nanostructured materials provide unique opportunities to provide stable properties up to the GHz and mm-Wave frequency ranges. In this paper, novel miniaturized nanostructured AMCs utilizing Barium Strontium Titanate (BST) thinfilms and ceramic-polymer composites are demonstrated through full-wave modeling analysis. The size reduction rates are 50.6 % when using 3 μm of BST thinfilm and 77 % when using 400 μm of ceramic-polymer composites. This concept can be further extended with high-permeability magnetic films, and thicker nanocomposite films to achieve further size and performance improvement for a variety of frequency bands and applications.

System Scaling With Nanostructured Power and RF Components

Abstract: The emergence of smartphones and other smart systems is driving new trends in electronics scaling that goes beyond transistors or active devices, to include all the system components such as packaging substrates, passive components, thermal structures, power sources, and the system interconnections. Current system components are at milliscale, creating a $10^{3}$ to $10^{6}$ scaling gap with the packaging interfaces at microscale, and transistors at nanodimensions. With current microstructured materials, component miniaturization also degrades performance metrics such as efficiency, tolerance or precision, thermal and frequency stability. Nanostructured materials and processes can potentially miniaturize these system components, while simultaneously enhancing the performance. These nanostructured components are assembled close to the active devices, resulting in ultraminiaturized and ultrathin systems with 3-D integration of passives with actives. This paper shows the impact of nanostructured materials toward enhancing the performance and miniaturization of power and radio-frequency (RF) passive components in emerging smart systems. Opportunities for nanostructured materials in improving the power density and efficiency of capacitors and inductors in power-supply modules are reviewed in the first part of the paper. The impact of nanostructured magnetic, dielectric and magneto-dielectric films on emerging RF subsystems is illustrated in the last part of the paper.

Machine-Learning Approach for Design of Nanomagnetic-Based Antennas

Abstract: We propose a machine-learning approach for design of planar inverted-F antennas with a magneto-dielectric nanocomposite substrate. It is shown that machine-learning techniques can be efficiently used to characterize nanomagnetic-based antennas by accurately mapping the particle radius and volume fraction of the nanomagnetic material to antenna parameters such as gain, bandwidth, radiation efficiency, and resonant frequency. A modified mixing rule model is also presented. In addition, the inverse problem is addressed through machine learning as well, where given the antenna parameters, the corresponding design space of possible material parameters is identified.

Reliability of Copper Through-Package Vias in Bare Glass Interposers

Abstract: Thermomechanical reliability of copper-plated through-package vias (TPVs) in ultrathin bare glass interposers was investigated through modeling, design, fabrication, reliability characterization, and failure analysis. Finite-element models were developed to analyze stress and strain distribution in TPV structures, and to obtain design guidelines for reliable TPVs. In order to experimentally validate the predictions of simulations, bare glass substrates of 100 $\mu \text{m}$ thickness with vias of 30 $\mu \text{m}$ diameter at 120 $\mu \text{m}$ pitch were metallized using Ti/Cu sputtering, followed by patterning and electroplating. Cu TPV daisy chains were fabricated and subjected to thermal cycling test between −55 °C and 125 °C to assess their thermomechanical reliability. Detailed cross-sectional analysis was also carried out by scanning electron microscope imaging of TPV cross sections. No electrical failures were detected in the Cu TPV chains. Failure analysis revealed copper delamination and crack formation in glass. The experimental reliability results are consistent with the thermomechanical models. Design and process recommendations are provided based on the modeling and experimental results.

Low-temperature, organics-free sintering of nanoporous copper for reliable, high-temperature and high-power die-attach interconnections

Abstract: A novel die-attach joining technique based on low-temperature film sintering of nanoporous Cu is demonstrated Nanoporous Cu films are proposed as a low-cost replacement of nano-sintering pastes with the following benefits: (i) synthesis by electrochemical dealloying, compatible with standard lithography processes; (ii) no organic content to minimize risks of voiding and corrosion; and (iii) controllable physical properties post sintering through tailorable initial nanostructure and morphology As a first proof-of-concept, thin films of nanoporous Cu with 25–50nm feature size and ∼60% relative density were synthesized by dealloying of Cu-Si films The nanoporous Cu films were then sintered on bulk Cu metallizations at temperatures of 200–250°C for 5–15min with an applied pressure of 6–9MPa, in reducing atmosphere A maximum shear strength of 42kgf was achieved and analysis of the fracture profiles showed failure through the sintered joints, confirming strong metallurgical bonding to bulk Cu Cross-sections of joints formed at 200°C and 250°C −15min observed by SEM showed relative density as high as 85%, achieved for the first time with sintered copper

3D system package architecture as alternative to 3D stacking of ICs with TSV at system level

Abstract: The 3D packaging started in 1970s for packaging of memory packages. Memory density has always been the bottleneck in high performance computing systems that led to two paths; increasing memory density within a chip in 2D and increasing by stacking many either packaged or bare chips in 3D. The barrier to systems performance, however, has been latency and bandwidth between logic and memory. 3D stacking of logic and memory has been viewed as the ultimate solution for a decade but it has its own barriers. While these barrier are being overcome by many approaches, the ultimate goal is to form miniaturized systems with highest performance and reliability at lowest cost. This paper presents a 3D system package architecture to address both bandwidth and other system requirements at system level in contrast to 3D ICs at device level.

Glass Interposer Electromagnetic Bandgap Structure for Efficient Suppression of Power/Ground Noise Coupling

Abstract: In this paper, we propose glass interposer electromagnetic bandgap (EBG) structure to efficiently suppress power/ground noise coupling. We designed, fabricated, measured, and analyzed a glass interposer EBG structure for the first time. Glass interposer EBG structure test vehicles were fabricated using a thin-glass substrate, low-loss polymer layers, and periodic metal patches with through glass vias (TGVs) in glass interposer power distribution network. Using the dispersion characteristics, we thoroughly analyzed and derived f L and f U of the glass interposer EBG structure. We experimentally verified that the proposed glass interposer EBG structure achieved power/ground noise suppression (below –40 dB) between f L of 5.8 GHz and f U of 9.6 GHz. Derived f L and f U based on dispersion analysis, full three-dimensional electromagnetic (3-D-EM) simulation and measurement achieved good correlation. In the glass interposer EBG structure, tapered structure of the TGV and thickness of the low-loss polymer used for metal-layers lamination affected the noise suppression bandgap significantly. The effectiveness of the proposed glass interposer EBG structure on suppression of the power/ground noise propagation and coupling to high-speed TGV channel was verified with 3-D-EM simulation. As a result, the proposed glass interposer EBG structure successfully and efficiently suppressed the power/ground noise propagation and improved eye-diagram of the high-speed TGV channel.

3D printed wearable flexible SIW and microfluidics sensors for Internet of Things and smart health applications

Abstract: In this paper, a flexible SIW wearable sensing platform is proposed with a novel 3D printing process which enables fast-prototyping customized wearable devices. The fabrication utilizes state-of-the-art SLA 3D printing that features fast prototyping of easy-to-reconfigure flexible 3D objects. Two different flexible metallization approaches are explored in this paper, which are complementary to each other and provide an excellent 3D metallization solution together. Two 3D shape SIW transmission lines are shown with a great flexibility and great potential for wearable devices. Moreover, based on a SIW slot waveguide antenna, this paper presents a proof-of-concept microfluidics sensor with sensitivity of 1.7 MHz/Er, which can be used as a wearable sensing device for real-time monitoring of body fluids. The proposed SIW-based flexible wearable devices along with the microfluidics sensors can be used in various Internet-of-Things applications, such as smart health and food quality monitoring.

Embedded Trench Redistribution Layers (RDL) by Excimer Laser Ablation and Surface Planer Processes

Abstract: This paper reports the demonstration of 2-5 µm embedded trench formation in dry film polymer dielectrics such as Ajinomoto build-up film (ABF) and Polyimide without using chemical mechanical polishing (CMP) process. The trenches in these dielectrics were formed by excimer laser ablation, followed by metallization of trenches by copper plating processes and overburden removal with surface planer tool. The materials and processes integrated in this work are scalable to large panel fabrication at much higher throughput, for interposers and high density fan-out packaging at lower cost and higher performance than silicon interposers.

Via-in-Trench: A Revolutionary Panel-Based Package RDL Configuration Capable of 200-450 IO/mm/Layer, an Innovation for More-Than-Moore System Integration

Abstract: This paper presents, for the first time, a novel silicon damascene like via-in-trench (ViT) interconnect for panel-scale package redistribution layer (RDL) configuration. The panel scale damascene RDL in this paper comprises of ultra-fine copper embedded trenches and microvias with diameter equal to the width of trenches using a 5 µm thick dry film photosensitive dielectric. A 140 µm thick glass substrate is used as the core material. The new panel scalable ViT interconnect is targeted for low cost, next generation 2D and 2.5D interposers and high density packages. The ViT RDL is integrated with 2 µm diameter microvias with 2.5 µm half-line pitch copper traces embedded in a 5 µm thick dry film photo-imageable dielectric (PID) polymer. This RDL integration directly translates to IO density of 200 IO/mm/layer. IO/mm/layer, as defined by Intel, is the number of wires routed per mm of die edge on each layer of package substrate. There is no capture pad required for ViT interconnect demonstrated in this paper. The routing Cu trace is aligned directly on top of microvia instead of the conventional via-capture pad-trace interconnect configuration. The fabrication of such a high density RDL is achieved by patterning a trench over via and then fully filling with copper. Conventional i-line (365 nm) photolithography, widely used for patterning PWB and package substrates, was employed for fine trenches formation as well as small microvias in the PID. An advanced 5 µm thick PID film IF4605 was selected for build-up layers. Experimental results showed that microvias with diameters of 2 µm and trenches with half-line pitch of 2.5 µm were achieved in 5 µm thick IF dry film. Traces with half-line pitch of 1 µm were demonstrated in a 3 µm thick liquid photo resist film. The aspect ratios were 2.5 for dry film PID and 3 for liquid photo-resist respectively. The best interconnection density in terms of IO/mm/layer was calculated to be 200 using dry film PID and can be extended to 450 using thinner PIDs. For comparison, the IO density for state-of-the-art organic interposer was 40 by using semi-additive process (SAP). The embedded trench technology breaks through the limit of SAP and achieves 5-10X interconnect density compared to SAP. The ViT interconnect is a revolutionary package RDL configuration to meet the requirements of future package substrates for high performance computing, high bandwidth memory and micro-miniaturized system applications. The demonstration of ViT RDL configuration on thin glass substrate with L/S/Via/Pitch of 2.5/2.5/2/20 µm using embedded trench approach will be presented and the fabrication processes will be described in detail.

Glass-Interposer Electromagnetic Bandgap Structure With Defected Ground Plane for Broadband Suppression of Power/Ground Noise Coupling

Abstract: In this paper, we propose glass-interposer (GI) electromagnetic bandgap (EBG) structure with defected ground plane (DGP) for efficient and broadband suppression of power/ground noise coupling. We designed, fabricated, measured, and analyzed a GI-EBG structure with DGP for the first time. The proposed GI-EBG structure with DGP is thoroughly analyzed using the dispersion characteristics and estimated stopband edges, $f_{L}$ and $f_{U}$ . We experimentally verified that the proposed GI-EBG structure with DGP achieved power/ground noise isolation bandgap (below −30 dB) between $f_{L}$ of 5.7 GHz and $f_{U}$ of 11 GHz. Estimation of $f_{L}$ and $f_{U}$ using dispersion analysis, full 3-D electromagnetic (EM) simulation results, and measurement results achieved good correlation. Effectiveness of the proposed GI-EBG structure with DGP on suppression of the power/ground noise coupling to high-speed through glass via (TGV) channel is verified with 3-D EM simulation. As a result, the proposed EBG structure successfully and efficiently suppressed the power/ground noise coupling and improved the eye diagram of the TGV channel. Lastly, we embedded thin alumina film in the proposed EBG structure and achieved even broader power/ground noise suppression between 2.1 and 14.7 GHz.

Substrate Embedded Thin-Film Inductors With Magnetic Cores for Integrated Voltage Regulators

Abstract: High-density and high-frequency inductors (>5 MHz) enable miniaturization of power modules, and also integration of voltage regulator modules into the processor packages for higher efficiency and switching frequencies Several advances in magnetic materials and substrate process integration are needed to meet the performance, size, and cost requirements This paper highlights two substrate-embedded inductor approaches using magnetic paste and pre-fabricated magnetic thick laminate sheets An innovative cavity-filling process using paste printing and hot pressing is developed to integrate magnetic paste with high magnetic filler loading into the core of standard organic laminate substrates The hot-pressed metal/polymer composite magnetic cores showed a permeability of ~55 at 10 MHz The other approach utilizes pre-fabricated thick magnetic sheets with a permeability of ~93 at 10 MHz Standard panel-scale processes are adapted for high-volume manufacturing at low cost The electrical performance of the inductors from both approaches showed good correlation between the simulated and measured data Compared with air-core inductors with the same structure, the advanced thin-film inductors with magnetic sheet showed nine times improvement in inductance Both these approaches can be scaled to higher frequencies with further innovation in magnetic composites

Reliability of Through-Package-Vias From via-First Processing With Ultra-Thin Glass

Abstract: Reliability of through-package vias (TPVs) in 100- ${\mu }\text{m}$ glass, prefabricated with an innovative via-first process, is investigated through systematic modeling, design, fabrication, and reliability characterization. Finite element models were built to assess the impact of this novel process on stress and strain distribution in TPV structures. Thermomechanical simulations were carried out to provide design guidelines for reliable TPVs. In order to experimentally validate the predictions from simulations, test samples containing metallized TPVs with 60 ${\mu }\text{m}$ diameter were fabricated with 100- ${\mu }\text{m}$ thick glass. To assess the reliability of TPVs, daisy chains were fabricated and subjected to thermal cycling between −55 °C and 125 °C. TPV daisy chain resistances were measured at regular thermal cycling intervals to detect initiation of failures during reliability characterization. As predicted from mechanical modeling, changes in resistance were experimentally observed to be less than the chosen failure criterion, indicating no failures. Detailed mechanical failure analysis by scanning electron microscopy revealed elimination of delamination and crack failures in contrast to those observed in via-first bare glass interposers. This is attributed to the reduced stress and enhanced adhesion with the polymer layers.

Integrated Copper Heat Slugs and EMI Shields in Panel Laminate (LFO) and Glass Fanout (GFO) Packages for High Power RF ICs

Abstract: This paper demonstrates, for the first time, ultra-thin, panel laminate fan-out (LFO) and glass fan-out (GFO) packages with embedded copper heat spreaders and electromagnetic shields for packaging high-power RF ICs in much smaller form factors and at potentially much lower cost than current ceramic and metal flange packages. This unique double-sided package addresses the thermal dissipation requirements of 30-100W power amplifiers by bonding the IC directly to a large copper heat spreader embedded in the substrate, using high thermal conductivity die-attach paste. It also addresses the RF, microwave and mm-wave performance requirements by utilizing low-loss tangent glass and polymer dielectrics, as opposed to lossy epoxy dielectrics or mold compounds. The combination of glass and high temperature polymers also enables superior harsh environment reliability with built-in stress buffer layers to mitigate the CTE mismatch induced stresses from large copper thermal structures.

Dielectric–electrode interactions in glass and silicon-compatible thin-film (Ba,Sr)TiO3 capacitors

Abstract: This paper investigates the role of electrode–dielectric interactions, and barrier materials on leakage current, breakdown voltage, yield and reliability of thinfilm (Ba,Sr)TiO3 capacitors on silicon and glass substrates. The first part of the paper investigates the electrode–dielectric interactions with sputtered Cu and Ni electrodes to identify the mechanisms that lead to high leakage current and low yield. The second part of the paper presents lanthanum nickel oxide as a viable solution to overcome the problems with sputtered Cu and Ni electrodes. A combination of low leakage current, high yield and capacitance densities was achieved with the oxide electrode systems.

Enabling Chip-to-Substrate All-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-Temperature Bonding

Abstract: This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) assembly. All-Cu interconnections are highly sought after to meet the escalating electrical, thermal, and reliability requirements of a wide range of emerging digital and analog systems. Such applications require low-cost processes with bonding temperatures and pressures ideally below 200°C and 20MPa, respectively, far from existing solutions established in wafer-level packaging. GT-PRC and its industry partners address this technology gap through innovative designs of bonding interfaces, introducing: 1) novel ultra-thin surface finish metallurgies applied on Cu bumps and pads to prevent oxidation and achieve low-temperature assembly, 2) low-cost fly-cut planarization technique to lower bonding pressures, and 3) low-modulus nanocopper foam caps to provide tolerance to non-coplanarities, and further reduce bonding temperatures and pressures.

Design and Demonstration of Highly Miniaturized, Low Cost Panel Level Glass Package for MEMS Sensors

Abstract: This paper describes an ultra-thin, low cost 3D glass sensor packaging platform for near-hermeticity with novel feedthrough and encapsulation technologies. Glass panels of thicknesses ranging from 50 µm to 300 µm are used which limits overall form factor to 10 MPa) and Dow Chemical's Benzocyclobutene (BCB) 14-P005 is found to be the best candidate for panel level glass-glass bonding. Modelling of the proposed three-layer glass packaging platform was performed in COMSOL Multiphysics. Results show a maximum deformation of about 2.3 µm - 2.5 µm in the BCB and GX-92 bonded package and the least average internal stress of 6.40 MPa in the BCB bonded package. The complete manufacturing cycle starting from cavity formation on bare glass to final 3D assembly to form the lidded/open cavity package including singulation is panel based, enabling significant cost reduction (depending on die dimensions and panel size) compared to ceramic and other substrate technologies.

Future of embedding and fan-out technologies

Abstract: Embedding is the most important strategic technology that is applicable for all digital, RF and power applications. When combined with fan-out at chip- and board-levels, it enables higher I/O applications. Embedded wafer fan-out (eWFO) is fabricated in either wafer fabs using BEOL tools, materials and processes, or OSAT's built-up fabs and tools. The eWFO from 300mm wafer fabs is capable of the ultimate I/O density but at high cost. The eWFOs from OSATs are capable of handling high I/Os from their 300mm fabs and the technology is extendable to panels. This technology is suitable for small devices such as RF. Embedding with or without fan-out is most suitable for power devices. They don't require high I/Os, but they need to be manufactured at very low cost. Ultra-large panels such as boards from PWB industry or LCD industry, are best suited to embed these devices. There is a need to couple ultra-high density of interconnections such as from wafer-based foundries with high-throughput panel manufacturing so as to end up with highest performance at lowest cost, even for larger ICs and packages and with very high I/O density. Two solutions are emerging: 1) panel-based embedding and fan-out manufacturing infrastructure, and 2) inorganic panel fan-out such as glass fan-out.

Experimental and Theoretical Assessment of Thin Glass Substrate for Low Warpage

Abstract: This paper compares the warpage after lead-free solder assembly of ultrathin glass and organic substrates for microelectronic packages. Smart mobile devices demand packages to be thinner, which exacerbates warpage, which in turn affects interconnect pitch scaling and reliability. Although low-coefficient-of-thermal-expansion (CTE) organic laminates have been developed to reduce the warpage during assembly, glass substrates offer added benefits of much higher modulus and thermo-mechanical stability, with the potential to reduce warpage beyond low-CTE organic materials. The focus of this paper is on modeling and measurements to quantify the warpage of glass and organic laminates at 100- $\mu \text{m}$ core thickness after thermo-compression bonding at 260 °C peak temperature. In the experiments, four-metal-layer glass substrates were fabricated at the panel level, diced into $18.4 \times 18.4$ -mm2 coupons, 10-mm $\times $ 10- $\text {mm}\,\,\times 630-\mu \text{m}$ silicon dies were thermo-compression bonded, and the warpage of the assembled packages was measured using shadow moire interferometry. In parallel to the experiments, numerical models that account for the viscoplastic behavior of the solder as well as the sequential build-up materials and processes have been developed. The predicted warpage from the models was compared to the experimental measurements. It was seen that the low-CTE glass had lower warpage than the organic core of equivalent CTE, while increasing the CTE of the glass increased the warpage. Also, the underfill fillet size was found to influence the warpage for thin substrate packages, and an optimal fillet size has been identified for minimizing warpage. B-staged and capillary underfill materials were compared and found to have similar warpage values.

Use of Birefringence to Determine Redistribution Layer Stresses to Create Design Guidelines to Prevent Glass Cracking

Abstract: Glass substrates have gained increasing attention for packaging due to their ideal material properties; however, the brittle nature of glass poses a challenge. This paper focuses on glass cracking due to dicing-induced defects and redistribution layer (RDL) stresses. RDL, which is composed of copper and dielectric polymer, creates stresses which become tensile at the exposed substrate glass edge due to the free edge effect and can cause crack propagation at low temperatures or when glass is exposed to water. The first part of this paper characterizes the difference in the secondary principal stresses induced in the glass by the RDL through birefringence measurements. The stress due to each material is individually calculated through finite element models by examining glass substrates with different thicknesses and copper distributions. The second part of this paper focuses on the reliability of glass substrates subjected to preconditioning and thermal cycling. In experiments, ten different glass substrate structures with thicknesses of 140–420 $ {\mu }\text{m}$ are subjected to −40 to 125 °C thermal cycling, finding that the thicker ( $ {\ge }120 ~{\mu }\text{m}$ total) build-ups exhibit cracking while the thinner build-ups ( $ {\le }80 ~{\mu }\text{m}$ total) do not crack. Models to predict crack propagation are developed using the stresses measured through birefringence and are validated to accurately predict the occurrence of crack propagation. In the last part of this paper, these models are used to develop design guidelines to prevent glass cracking due to RDL stresses and dicing-induced defects. These guidelines specify the allowable dicing defect size and build-up thickness combinations to prevent glass cracking based on the energy release rate observed during the thermal cycling experiments. The critical levels for the energy release rate for crack propagation and no crack propagation were $ {G = 1.05}$ J/ $\text{m}^{2}$ and $ {G = 0.87}$ J/ $\text{m}^{\mathbf{2}}$ , respectively. Allowable dicing defect size and build-up thickness are found to be inversely proportional and it is generally recommended to keep the total build-up thickness at or below 80 $ {\mu }\text{m}$ .

Analysis of System-Level Reliability of Single-Chip Glass BGA Packages with Advanced Solders and Polymer Collars

Abstract: Emerging high-performance computing systems have been aggressively driving advances in packaging technologies to meet their escalating performance and miniaturization needs. Large, high-density 2.5D silicon interposers have gained momentum with the recent split-die trend but face critical reliability challenges at board-level that are addressed by introducing an additional organic BGA package between interposer and board. Glass substrates have emerged as a promising alternative owing to the superior electrical properties, sub-5µm lithographic capability and tunable CTE of glass that enables direct SMT assembly to mother boards among other advantages. This paper investigates board-level reliability of single-chip glass BGA packages, 18.5mm × 18.5mm in body size and 100µm in thickness at 400µm BGA pitch. A parametric finite-element analysis was performed to extract the optimum glass CTE for balanced chip-and board-level reliabilities. Innovative doped solder materials and strain-relief mechanisms were evaluated to improve board-level reliability with minimum system-level impact. Daisy-chain test vehicles with low (3.3ppm/K) and high (9.8ppm/K) CTE glass substrates were fabricated and assembled at chip and board levels by Cu pillar thermocompression bonding and standard SMT reflow, respectively. Assemblies with different BGA solder alloys, SAC105, SAC305 and Indium's Mn-doped SACmTM, were subjected to thermal cycling test according to JEDEC standards. Comprehensive failure analysis was performed to evaluate fatigue life improvements with advanced interconnection materials and conclude on scalability of glass substrates for high-performance applications.

Via-First Process to Enable Copper Metallization of Glass Interposers With High-Aspect-Ratio, Fine-Pitch Through-Package-Vias

Abstract: A via-first process for metallizing copper on glass substrates is presented using a thin, patternable polymer film, electroless copper deposition, and semiadditive processing. A procedure for partially precuring the polymer was developed in order to achieve a tented via structure after dry-film lamination and curing. The flexibility of the process is demonstrated by the use of plasma etching, CO2, and UV laser ablation as patterning technologies. Metallization by electroless copper deposition and semiadditive processing is shown to be conformal, continuous, and without defects on the surface and in the vias as demonstrated by cross-sectional analysis. Glass of $100~\mu \text{m}$ thickness with vias of 10– $20~\mu \text{m}$ diameter and $40~\mu \text{m}$ pitch was metallized to demonstrate the dimensional capability of the process. Thermomechanical reliability was validated by copper peel testing after highly accelerated stress testing and daisy-chain resistance measurements taken throughout thermal cycle testing.

High Frequency Electrical Performance and Thermo-Mechanical Reliability of Fine-Pitch, Copper-Metallized Through-Package-Vias (TPVs) in Ultra-Thin Glass Interposers

Abstract: This paper demonstrates the high frequency performance and thermo-mechanical reliability of through vias with 25 µm diameter at 50 µm pitch in 100 µm thin glass substrates. Scaling of through via interconnect diameter and pitch has several electrical performance advantages for high bandwidth 2.5D interposers as well as mm-wave components for 5G modules. This paper focuses on the assessment of thermo-mechanical reliability, of high aspect ratio TPVs at ultra-fine pitch, metallized using a via–first approach, and the accurate electrical modelling of TPVs and transmission lines with TPVs up to 40 GHz, using ANSYS HFSSTM. Test vehicles consisting of through via daisy chain structures were designed and fabricated on 100 µm thick glass, laminated with a 5 µm epoxy dry film polymer on both sides. Fine pitch TPV arrays were subjected to Thermal Cycle Testing (TCT) between -55 °C and 125 °C, and the majority of TPV chains passed 1000 cycles with less than 15% change in DC resistance. The impact of pitch scaling on the reliability was studied by varying the spacing of neighboring TPVs using 3D quarter-symmetric finite element models. A novel approach based on wave dimensional analysis was investigated to accurately capture the electrical parasitics of the vias in mm wave frequency bands. The resistance and inductance of a single signal TPV at 28 GHz were estimated to be 93 m and 60 pH respectively. Using Voltage Standing Wave Ratio (VSWR) calculations, it was shown that smaller via diameters are preferable for transitions from a 50 impedance matched planar to vertical interconnection.

Embedded Trench Redistribution Layers at 2– $5~\mu \text{m}$ Width and Space by Excimer Laser Ablation and Surface Planer Processes for 20– $40~\mu \text{m}$ I/O Pitch Interposers

Abstract: This paper reports on one of the first demonstrations of the formation and metallization of 2–5- $\mu \text{m}$ lines and spaces by an embedded trench method in two dry-film polymer dielectrics, Ajinomoto build-up film and preimidized polyimide, without using chemical mechanical planarization. The trenches and vias in 8–15- $\mu \text{m}$ -thick dry-film dielectrics were formed by 308-nm excimer laser ablation, followed by the metallization of the trenches and vias by copper electrodeposition. A low-cost planarization process was used to remove the copper overburden with a surface planer tool. Using an optimized set of materials and processes, multilayer redistribution layers with 2– $5~\mu \text{m}$ trenches and vias were successfully demonstrated. Although thin film processes on silicon wafers have been able to achieve 40- $\mu \text{m}$ I/O pitch for interposers, the materials and processes integrated in this paper are scalable to large panel fabrication at much higher throughput, for interposers and high-density fan-out packaging at lower cost and higher performance than silicon interposers.