Showing papers by "Rao Tummala published in 2018"

First Demonstration of Compact, Ultra-Thin Low-Pass and Bandpass Filters for 5G Small-Cell Applications

Abstract: Package-integrated and ultra-thin low-pass filter (LPF) and bandpass filter (BPF) with footprint smaller than $0.5\lambda _{0}\times 0.5\lambda _{0}\times 0.025\lambda _{0}$ at the operating frequencies of 28- and 39-GHz bands are presented for 5G and mm-wave small-cell application. Such package integration of 5G filters with ultrashort 3-D interconnects allows for low interconnect losses that are similar to that of on-chip filters, but low component insertion loss of off-chip discrete filters. These thin-film filters exhibit a cross-sectional height of $188.5~\mu \text{m}$ and can be utilized either as embedded components or integrated passive devices in module packages. Three topologies of LPF and BPF in total are modeled, designed, and fabricated on precision thin-film buildup layers on glass substrate as a core. Large-area panel-compatible semiadditive patterning (SAP) process is utilized to form high-precision topologies to aid the low-cost fabrication of ultraminiaturized filters. SAP also enables the realization of ultra-thin traces to precisely model high-impedance inductive lines compared to conventional subtractive etching and printing techniques. This results in filters with low insertion loss, low VSWR, and high selectivity. The simulated and measured results of filters show an excellent correlation.

Miniaturized High-Performance Filters for 5G Small-Cell Applications

Abstract: This paper demonstrates the first panel-based ultra-miniaturized filters with footprint smaller than half of the free-space wavelength at the operating frequencies of 28 and 39 GHz bands for 5G and mm-wave small-cell applications. The thin-film filters can be utilized either as ultra-thin integrated passive devices (IPDs) or embedded into the module substrates. Two filter types: lowpass and bandpass, with three topologies in total, are modeled, designed and fabricated on precision thin-film build-up layers on glass and traditional laminate cores. The modeling, design and optimization phase included the considerations of fabrication tolerances and testability of the filters. Glass is an ideal core material for mm-wave 5G modules and IPDs since it combines the benefits of ceramics for high frequency electrical performance, laminates for large panel processing and low cost, silicon-like dimensional stability and precision patterning, which is essential for mm-wave circuits. Unlike printing used in ceramics, or subtractive etching used in multilayer organics (MLO), this research utilizes semi-additive patterning (SAP) process to form high precision, multilayer redistribution layers (RDL) to design ultra-compact filter topologies with low insertion loss and improved stopband rejection, due to the close-to-ideal translation of lumped-to-distributed components. The simulated results of bandwidth, in-band insertion loss and out-of-band rejection of filters show excellent correlation with the measured results.

2.5D Glass Panel Embedded (GPE) Packages with Better I/O Density, Performance, Cost and Reliability than Current Silicon Interposers and High-Density Fan-Out Packages

Abstract: This paper demonstrates for the first time a next generation high-bandwidth 2.5D glass panel embedding (GPE) architecture with better I/O density, performance, cost and reliability than silicon interposers and high density fan-out packages for heterogeneous integration. Silicon interposers were the first 2.5D technology to enter volume manufacturing, first with TSVs as CoWoS by TSMC and later as embedded bridge EMIB by Intel. High density fan-out packages by chip-first, such as InFO by TSMC, and RDL-first were recently developed. However, all current approaches face challenges in meeting future 2.5D I/O, performance, cost and reliability needs. This paper presents the first demonstration of a revolutionary new concept in scaling power-efficient bandwidth, cost, large package size and board-level reliability, called 2.5D glass panel embedding (GPE). High temperature and low CTE glass reduces die shifts from tens of microns in current molded fan-out to less than 2 microns in GPE. RDL connecting to embedded ICs with 1-2 micron lines and vias overcomes the solder thermo-compression bonding limitations. RDL with much lower resistance and capacitance than BEOL RDL continues power-efficient bandwidth scaling. Ultra-thin glass is readily available in large panels for lower cost. The tailorable CTE of glass allows for reliable direct SMT attach to board of large GPE packages. With a total package thickness of less than 200 microns, this paper describes the fabrication process for an ultra-thin 2.5D GPE, and a systematic parametric process optimization to reduce die shifts to less than 2 microns, leading to the first known demonstration of side-by-side embedding of HBM test chips with all-Cu interconnections at 40 micron I/O pitch.

Leading-Edge and Ultra-Thin 3D Glass-Polymer 5G Modules with Seamless Antenna-to-Transceiver Signal Transmissions

Abstract: This paper demonstrates seamless antenna-to-transceiver signal transitions on panel-scale processed ultra-thin glass-based 5G modules with impedance-matched transmission lines and microvias with high-precision low-loss re-distribution layer design and fabrication, for high-speed 5G communication standards at the 28 GHz band. In order to demonstrate the benefits of glass for 5G communications, various types of transmission lines and high-gain and high-bandwidth package-integrated antennas were modeled and designed on ultra-thin glass substrates with low-loss dielectric thin-films, for highest bandwidth and efficiency in the mm-wave bands. The simulated results for insertion losses of transmission lines (i.e., microstrip lines and striplines) and microvia transitions are correlated with the measured values on the thin glass substrates. In addition to the low-loss signal transitions from chip to antenna, package-integrated Yagi-Uda antennas are modeled and designed, resulting in a realized gain of higher than 4 dBi/element with a bandwidth higher than 20%. The mm-wave electrical performance of glass substrates was benchmarked with existing 5G candidates such as organic laminate substrates and fanout wafer level packaging. Along with the reduction in the overall package foot-print, reduction in link-budget losses is shown to be feasible with the proposed 3D glass packages.

Ultrathin High- $Q$ 2-D and 3-D RF Inductors in Glass Packages

Abstract: Embedded inductors in ultrathin glass substrates were modeled, designed, fabricated, and characterized. Various 2-D and 3-D topologies were explored to obtain the tradeoffs in inductance density, quality ( ${Q}$ ) factor, size, and self-resonant frequency (SRF). Single-layer spiral inductors were modeled and designed to formulate an inductor library that is optimized for high inductance densities. These include variations in the number of turns, conductor linewidth and spacing, and the ratios of inner diameter and outer diameter of the spiral. In order to optimize the inductor topology for higher ${Q}$ factors, various types of 3-D topologies with 300- $\mu \text{m}$ glass were studied through modeling, fabrication, and model validation. Inductance densities, ${Q}$ , and SRF were measured for various topologies. Higher inductance densities of 10–20 nH/mm2 with a ${Q}$ factor of 30–40 are obtained for spiral inductors on glass, making them more suitable for module miniaturization when ${Q}$ -factor requirements are not stringent. For higher ${Q}$ factors, 3-D solenoid and daisy-chain topologies are found to be more suitable in spite of their low inductance densities of 3 nH/mm2, making them a better choice for applications where better channel selectivity, precise phase-switching, and lower insertion loss are needed.

Capillary Performance of Micropillar Arrays in Different Arrangements

Abstract: In this study, permeability and capillary pressure of copper micropillar structures (height: 50 µm, diameter: 50 µm) in different arrangements (hexagonal, rectangular, and square) and different por...

Novel 3D-/Inkjet-Printed Flexible On-package Antennas, Packaging Structures, and Modules for Broadband 5G Applications

Abstract: Additively manufacturing techniques including 3D and inkjet printing is used to fabricate antenna and packaging structure at mm-wave range for 5G applications. The 3D printed flexible material, FLGR02, is applied to the flexible mm-wave packaging application. The fabrication process and material characterizations including solutions to surface treatment for ink adhesion, smooth of surface roughness, and CTE mismatch between the flexible material and the silver ink are proposed. Then the proposed process is used to fabricated a broadband 5G on-package antenna. The measured S11 of the proposed on-package antenna is smaller than -10 dB from 22.4 GHz to 30.1 GHz. Besides, the measured realized gain is larger than 5 dB from 22 GHz to 30.5 GHz. The differences of realized gain within the operational bandwidth is smaller than 3 dB. The fractional bandwidth is 29.3 %. The proposed antenna is broadband enough to cover the whole 5G band from 24.5 GHz to 29.5 GHz. The size of the antenna is 5mm×9mm which is 0.44?0 × 0.79?0. The radiation patterns within the operational band is also measured. Finally, a proof-of-concept demonstration of SoP design is fabricated.

Heterogeneous and homogeneous package integration technologies at device and system levels

Abstract: Moore's law scaling has been the primary focus in the last 60 years towards System-On-Chip. This has resulted in an industry-driven, device-level integration to a 50 billion transistor chip, incorporating progressively more and more functions in a single die, along with cost reduction from node to node. However, as Moore's law approaches limits in combined scaling and cost reduction, there is an unparalleled opportunity for package integration to enable better devices in the short term and to enable better systems in the long term, both by homogeneous and heterogeneous integrations. This paper presents the package integration evolution to the current approaches at device and system-levels. It then presents Georgia Tech's vision in advancing package integration at device-level by extending the on-going 2D, 2.5D, and 3D architectures as well as proposing an entirely new approach to materials, processes, and architectures at both device and system-levels. Both are enabled by ultra-thin packaging with TSV-like through vias in the passive substrates rather than in the logic ICs. At system level, it proposes and develops a 3D architecture that combines both package and system functions into an ultra-miniaturized, highly integrated, and highly reliable system package with ultra-short and ultra-high bandwidth interconnections with ultra-high reliability.

Design and demonstration of Glass Panel Embedding for 3D System Packages for heterogeneous integration applications

Abstract: This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integrati...

Reliability Studies of Excimer Laser-Ablated Microvias Below 5 Micron Diameter in Dry Film Polymer Dielectrics for Next Generation, Panel-Scale 2.5D Interposer RDL

Abstract: This paper demonstrates the thermal cycling reliability of 4 µm diameter microvias using an ultra-thin dry film ABF, a non-photosensitive dielectric material. Such via scaling in conjunction with line scaling to achieve silicon BEOL-like RDL densities is required for the next generation of interposers. The dry film dielectric, ABF, is an epoxy-silica filler based material. This is an ideal material for a double-sided, panel-scale compatible electroless copper seed metal deposition process. The test vehicle consisting of daisy chain structures used for the reliability studies was fabricated by an excimer laser dual damascene process. The trenches for the daisy chain line and pad structures were first formed in a novel dry film ABF material. Microvias with diameter of 4 µm were then ablated in the film. The stepper system of the excimer laser allowed sub-micron alignment accuracy for the via structures. Two different capture pad structures were used to land the microvias. The 4 µm diameter microvias were landed in 4 µm width and 5 µm width capture pad structures. A panel-based electroless copper seed metal deposition process was used to form a conductive layer on the polymer film. The desmear process during the electroless deposition increased the microvia diameter to 5 µm and the capture pad widths to 5 µm and 6 µm respectively. The structures were filled by conventional electrolytic plating process and overburdened to a thickness of 5 µm. The panel-scalable Surface Planar DFS8910 tool was used to fly-cut 1 µm deep into the polymer and achieve the final circuitry. The challenges of this mechanical fly-cut process with filler based ABF materials and removal of complete electroless copper seed from the polymer anchors will be discussed. The resistance of the daisy chain structures containing an array of 400 microvias was measured after the planarization process. A yield of 88 % was achieved on a 300 mm wafer with 4 µm microvias and 5 µm capture pad structures with excellent daisy chain resistance. The samples were then exposed to: (A) 1000 liquid-to-liquid thermal shock cycles with a dwell time of 5 mins each at 125 °C and -55 °C and (B) 1000 air-to-air thermal cycles from -55 °C to 125 °C with a dwell time of 15 mins at each temperature node and a total cycle time of 1 hour. The resistances after thermal cycling tests showed an average increase of < 5 %, well within the 10 % resistance change criteria.

Multilayered Electromagnetic Interference Shielding Structures for Suppressing Magnetic Field Coupling

Abstract: Control of electromagnetic interference (EMI) represents a major challenge for emerging consumer electronics, the Internet of Things, automotive electronics, and wireless communication systems. This paper discusses innovative EMI shielding materials and structures that offer higher shielding effectiveness compared with copper. To create high shielding effectiveness in the frequency range of 1 MHz to 100 MHz, multilayered shielding topologies with electrically conductive and nanomagnetic materials were modeled, designed, fabricated, and characterized. In addition, suppression of out-of-plane and in-plane magnetic-field coupling noise with these structures is compared with that of traditional single-layer copper or nickel–iron films. Compared with single-layered copper shields, multilayered structures consisting of copper, nickel–iron, and titanium showed a 3.9 times increase in shielding effectiveness in suppressing out-of-plane or vertically coupled noise and 1.3 times increase in lateral coupling. The superiority of multilayered thin-film shields over conventional shielding enables greater design flexibility, higher shielding effectiveness, and further miniaturization of emerging radiofrequency (RF) and power modules.

Next Generation of Automotive Radar with Leading-Edge Advances in SiGe Devices and Glass Panel Embedding (GPE)

Abstract: The design and process building blocks for an ultra-miniaturized automotive radar module were demonstrated with the most leading-edge SiGe devices operating at 77 GHz and 3D glass panel embedded (GPE) package. The key advances with such a package include: 1) advanced SiGe BiCMOS 77 GHz automotive radar receiver with improved detection range and signal-to-noise ratio (SNR), 2) ultra-miniaturized module and low-loss interconnections by GPE packaging, 3) improved board-level reliability enabled by the tailorability of the CTE of the glass panels and compliant interconnections, 4) innovative chip-package co-design and 5) large area panel-scalable glass substrate processes for potentially lower cost. To demonstrate this automotive radar module, low-noise amplifier (LNA) and mixer chips for 77 GHz automotive radar receiver were first designed, and then fabricated using IBM 8HP 130nm technology with the size of 5mm x 5mm and thickness of 250 µm. Glass panels with 300 µm thickness and through glass cavities were fabricated with cavity location and dimensional accuracy below +5 µm, and then then bonded on a 100 µm thick glass panel carrier using adhesive bonding. After glass-to-glass bonding, the designed 77GHz radar chips were placed in the glass cavities using a high-speed placement tool from Kulicke and Soffa. RDL polymers were then laminated and cured on both sides to minimize the warpage of package. A UV laser tool from ESI was then used to drill the microvias to interconnect the chip to the fan-out RDL layer by a standard semi-additive process (SAP). Initial modeling and measured results indicate the potential for an ultra-miniaturized automotive radar module with high-linearity, low noise figure below 10dB and low-loss chip-package interconnection.

An Advanced Photosensitive Dielectric Material for High-Density RDL with Ultra-Small Photo-Vias and Ultra-Fine Line/Space in 2.5D Interposers and Fan-Out Packages

Abstract: In this paper, we introduce an advanced photosensitive dielectric material (PDM) we recently developed to realize a high resolution and low coefficient thermal expansion (CTE) for next-generation high-density re-distribution layer (RDL) for 2.5D interposer and high-density fan-out package applications. For high-density RDL, photosensitive materials need to have (1) a high resolution, (2) high insulation reliability and (3) semi-additive process (SAP) compatibility. We have developed an advanced photosensitive dielectric material witch meets these three requirements. We demonstrate ultra-small via (3 um) by i-line stepper. For SAP compatibility, we have fabricated copper traces of 2um lines and spaces on the PDM by using SAP with sputtered Ti/Cu seed layer. The insulation reliability test was performed at the condition of Bias-Highly Accelerated-Stress Test, 135 deg.C. 85% R.H. on test coupon with 5um thick PDM. As a result, over 300 hours insulation reliability was confirmed. These results mean that the newly-developed PDM is suitable for next generation 2.5D interposer and high-density fan-out package applications. In terms of a package reliability, a low CTE and low process temperature are desired. In order to reduce the CTE of the material and maintain high resolution, nano-size fillers were integrated into the material. As a result, CTE of 30-35 ppm / deg.C was achieved. Curing temperature of the PDM is designed at 180 deg.C which is lower than most of the advanced dielectric materials. These two features contribute to reduce warpage of high density substrates and interposers, so it is expected to be applied to multiple layer application. We also fabricated test coupon with daisy chain structure connected by ultra-small vias and very stable via resistance was confirmed. In conclusion, our newly-developed PDM is a promising dielectric material for highly reliable high-density redistribution layer (RDL) for 2.5D interposers and fan-out package applications.

Low Cost Panel-Based 1-2 Micron RDL Technologies with Lower Resistance than Si BEOL for Large Packages

Abstract: This paper presents the latest lithographic advances to enable scaling of packaging redistribution layer (RDL) feature size towards 1-2 µm line and space on panel-based glass substrates. Critical dimension (CD) of 1 µm line and space with aspect ratio (AR) of 5 was demonstrated in a newly developed chemically amplified plating photoresist by using i-line contact mask aligners and low numerical aperture (NA) 1x projection steppers. The minimum line and space demonstrated was 0.9 µm with AR of 5.5. Such high AR package RDL has much lower trace resistance compared to silicon back-end-of-line (BEOL) RDL, enabling power-efficient higher bandwidth. The relationship between resolution (R) and depth-of-focus (DOF) for low NA projection stepper is discussed. Low cost, low NA, large field steppers are better suited to large panel and large size package fabrication. A cost-effective mechanical fly-cut process was implemented for planarization of the entire wafer or panel with < 1 µm flatness that ensures the success of 1 µm with AR of 5 lithography by using low cost lithographic tools.

Integrated Copper Heat Spreaders in Glass Panel Embedded Packages with Near-Zero Thermal Interface Resistance

Abstract: Ultra-thin, panel embedded packages in glass and laminate substrates with embedded copper heat-spreaders with near-zero thermal interface resistance are demonstrated for the first time. This unique package addresses the thermal dissipation requirements of 30W-100W power amplifiers by embedding the IC in the glass substrate and direct metallization with large copper heat spreaders. This package also demonstrates a solution to mitigate the stresses induced from copper-glass CTE mismatch using built-in stress buffers. Ultra-low loss dry film polymers used to embed the IC and serve as the RDL dielectrics result in low loss at GHz frequency bands.

Organic Damascene Process for 1.5- $\mu$ m Panel-Scale Redistribution Layer Technology Using 5- $\mu$ m-Thick Dry Film Photosensitive Dielectrics

Abstract: This paper presents a novel organic embedded trace damascene redistribution layer (RDL) process for panel-scale 2.5-D interposers and high-density fan-out package (HDFO) substrates. A minimum feature size of 1.5- $\mu \text{m}$ line and space using ultrathin polymer dielectrics on glass, silicon, and as well as on organic laminate was demonstrated. This is the first demonstration of a complete set of materials and processes that can be applied to large glass or organic panels, to bridge the interconnect gap between current semiadditive process (SAP) RDL and wafer back-end-of-line (BEOL) RDL. The ultra-fine pitch multilayer RDL structures demonstrated in this paper achieve an optimum balance of high IO density, high electrical performance, and low process costs. IO density in terms of IOs per mm per layer, as defined by Intel, refers to the number of traces routed per millimeter of die edge on one RDL layer of an interposer or package substrate. The current SAP technology can achieve an IO density of about 40 IOs/mm/layer on 510 mm $\times \,\, 510$ mm organic laminate panels. The challenges of fabricating copper metal traces below 5 $\mu \text{m}$ width and 5 $\mu \text{m}$ space using conventional SAP are discussed. On the other hand, wafer-based BEOL damascene RDL technology can scale to IO densities of greater than 200 IOs/mm/layer, but at relatively higher costs on 300-mm-diameter round wafers. An additional challenge for silicon interposers is low die-to-die interconnect data rate of single copper trace due to the high resistance of BEOL RDL structure. A combination of larger cross-sectional area with high aspect ratio (AR) is preferred for low-resistance, high-bandwidth escape routing traces. In this paper, the materials and process flow of embedded trace damascene RDL technology featuring trenches of 1.5 $\mu \text{m}$ width and 1.5 $\mu \text{m}$ space with AR of 2–4 will be described. A new 5- $\mu \text{m}$ -thick dry film photosensitive polymer dielectric IF4605 was used for the trench layer as well as the via layer. A large panel-scalable Surface Planar DFS8910 tool was used to achieve a highly planar metal–polymer RDL surface, at potentially lower costs than chemical-mechanical polishing that has been used in prior work. The processes discussed in this paper will enable routing of fine copper traces on panel-based interposers and HDFOs at higher throughput and potentially lower costs than BEOL processes. A two-metal layer, 20- $\mu \text{m}$ IO pitch silicon-like RDL test vehicle was fabricated with 2.5- $\mu \text{m}$ -wide and 2.5- $\mu \text{m}$ -space embedded traces and integrated with 2- $\mu \text{m}$ -diameter microvias using IF4605 on glass. There was no pad in the integration. This pad-less structure can be used for achieving theoretically maximum interconnect density. The process flow emulates the salient features of damascene processes used for BEOL RDL on semiconductor wafers, but simplifies them using dry film polymer materials and panel processes. Hence, it is referred to as organic embedded trace damascene or simplified as an organic damascene process (ODP) in this paper. The novel ODP interconnect addresses the current limitations of both SAP and BEOL processes. The key highlights of this new ODP technology are: 1) IO densities of 200 IO/mm/layer or more; 2) via-to-via pitch of $20~\mu \text{m}$ or less; 3) high AR of routing traces in the range of 2–4; 4) precise RDL linewidth control; 5) double-sided process with glass core; and 6) reduced number of process steps and panel-scalability leading to lower fabrication costs.

High-Temperature And Moisture-Ageing Reliability of High-Density Power Packages For Electric Vehicles

Abstract: Reliability and failure mechanisms associated with high-density, high-temperature (175-250 °C) electronics in harsh environments were investigated. Test-structures were built to emulate both high-power and high-density packages. Different material sets were evaluated for various failure modes such as delamination and corrosion. Design guidelines for high-density and high-power automotive packages are provided with emerging and leading-edge packaging materials. A 40% reduction in the adhesion strength was seen after high-temperature ageing at 200 °C along with a discoloration of the polymer. The experimental results indicate a need for enhanced interfaces and improved material properties for long-term high-temperature reliability.

Ultra-High Density, Thin-Film Tantalum Capacitors with Improved Frequency Characteristics for MHz Switching Power Converters

Abstract: High-density passive components are needed for continued miniaturization of complex high-performance electronic systems. Tantalum (Ta) capacitors provide some of the highest volumetric densities achieved due to their combination of high-surface area and relatively high dielectric constant, but suffer from low frequency stability and large form-factors due to the electrode design. In this paper, a printed thin-film tantalum capacitor design is presented. Tantalum capacitor arrays of 1 μF/mm2 up to and beyond 1 MHz. The improved frequency stability comes from the ultra-thin structure of the capacitors, which reduces the path length of the charging and discharging current. The capacitors showed low equivalent series resistance and consistent electrical performance before and after thermal moisture testing at 65°C and 95% relative humidity for 500 h and 1000 h. Due to the ultra-low form-factor, the thin-film Ta capacitor technology can be extended to highly-miniaturized power converters with efficient substrate- or wafer-scale integration.

First Demonstration of Silicon-Like >250 I/O Per mm Per Layer Multilayer RDL on Glass Panel Interposers by Embedded Photo-Trench and Fly Cut Planarization

Abstract: This paper demonstrates for the first time >250 I/O per mm per layer on glass panels utilizing embedded photo-trench and fly cut planarization processes to meet the demands of next generation high bandwidth 2.5D Interposers. This paper combines the use of novel photo-imageable dielectrics developed by TOK and advances in Disco's Fly-Cut planarization technique to deliver unit processes capable of delivering >250 I/O per mm per layer.

Nanopackaging for Component Assembly and Embedded Power in Flexible Electronics: Heterogeneous Component Integration for Flexible Systems

Abstract: The trends to high-density, ultrathin, and low-cost electronic systems are currently changing the face of the mobile, security, health-care, and automotive industries. Providing a flexible platform extends the applicability of these next-generation circuits to smart displays, conformal sensors, Internet of Things (IoT) tags, remote health-monitoring systems, radar and millimeter (mm)-wave electronics, among others. As a result, the total market for f lexible, organic, and printed electronics is projected to grow from close to US$30 billion in 2017 to approximately US$75 billion in 2027 [1]. Major applications that drive the field of flexible and printed electronics are illustrated in Figure 1.

Demonstration of Patternable All-Cu Compliant Interconnections with Enhanced Manufacturability in Chip-to-Substrate Applications

Abstract: Emerging 2.5D and 3D package architectures for next-generation high-performance computing and digital applications require high-performance off-chip interconnections at ultra-fine pitch of less than 20µm. All-Cu interconnections are highly desirable as they have excellent electrical and thermal properties. However, current Cu-Cu fine-pitch bonding technologies have limited manufacturability, require special bonding conditions and are mainly limited to wafer-level packaging. A novel approach to realize all-Cu interconnections for chip-to-substrate assembly, utilizing patternable nanoporous copper (np-Cu) foam caps on copper pillars is presented in this paper. The np-Cu foam caps have low modulus to provide tolerance to non-coplanarities, and have very high surface energy which enables assembly at low-temperatures and pressures. The patterned np-Cu films were fabricated by chemical dealloying of co-electroplated Cu-Zn films, using standard semi-additive processing techniques. The patterned foam films were bonded to bulk-Cu at bonding temperature of 250oC for 30min with an applied pressure of 9MPa. During assembly, the np-Cu foams densified and formed good metallurgical contact with the bulk-Cu to achieve a void-free interface.

Electroanalytical Study of Organic Additive Interactions in Copper Plating and Their Correlation with Via Fill Behavior

Abstract: In this study, individual interactions between various classes of organic additives in electrolytic copper plating solutions are characterized by electroanalytical methods. Cyclic voltammetry and chronopotentiometry were used to compare cases of sequential and competitive adsorption of additive combinations to the Cu cathode. Of the polyalkylene glycol (PAG) suppressors investigated, polypropylene glycol was in general a weaker suppressor than polyethylene glycol, showing weaker polarization of the Cu cathode and faster depolarization when combined with bis(sodium sulfopropyl)disulfide (SPS). The rapid depolarization of PAG with SPS resulted in a conformal Cu filling behavior in blind-vias. By itself, the leveler molecule polyvinyl pyrrolidone (PVP) shows very weak and slow suppression compared to the PAG-type suppressors, but depolarization of the Cu cathode is prevented when combined with SPS. The weak polarization of PVP combined with SPS resulted in sub-conformal filling behavior in blind-vias. The potential response of SPS, PAG, and PVP combined was found to be the sum of their individual interactions: PAG adsorbs rapidly to strongly polarize the cathode, but PVP prevents depolarization with time from SPS. This strong and consistent polarization outside the vias resulted in a superconformal filling behavior, with more than twice the thickness of Cu plated in the vias than outside.

Reliability of fine-pitch through-vias in glass interposers and packages for high-bandwidth computing and communications

Abstract: Glass is an ideal substrate material to enable 2.5D and 3D packaging of ICs at low cost and high performance. However, it is a brittle material and is prone to failures during fabrication and operation. Large coefficient of thermal expansion (CTE) mismatch between copper and glass leads to thermomechanical stresses that can lead to glass cracking and delamination from glass interfaces. This paper focuses on modeling and reliability characterization of copper-plated through-package-vias (TPV) in glass packages. Thermomechanical simulations were carried out to obtain design guidelines for reliable TPVs in glass. Test-vehicles with different glass thicknesses and copper TPV fabrication conditions were fabricated for thermal cycling tests, resistance monitoring and failure analysis. The reliability characterization results showed good thermomechanical reliability of TPVs in ultra-thin glass panels.

Accelerated Metastable Solid–liquid Interdiffusion Bonding with High Thermal Stability and Power Handling

Abstract: Emerging high-performance systems are driving the need for advanced packaging solutions such as 3-D integrated circuits (ICs) and 2.5-D system integration with increasing performance and reliability requirements for off-chip interconnections. Solid–liquid interdiffusion (SLID) bonding resulting in all-intermetallic joints has been proposed to extend the applicability of solders, but faces fundamental and manufacturing challenges hindering its wide adoption. This paper introduces a Cu-Sn SLID interconnection technology, aiming at stabilization of the microstructure in the Cu6Sn5 metastable phase rather than the usual stable Cu3Sn phase. This enables formation of a void-free interface yielding higher mechanical strength than standard SLID bonding, as well as significantly reducing the transition time. The metastable SLID technology retains the benefits of standard SLID with superior I/O pitch scalability, thermal stability and current handling capability, while advancing assembly manufacturability. In the proposed concept, the interfacial reaction is controlled by introducing Ni(P) diffusion barrier layers, designed to effectively isolate the metastable Cu6Sn5 phase preventing any further transformation. Theoretical diffusion and kinetic models were applied to design the Ni–Cu–Sn interconnection stack to achieve the targeted joint composition. A daisy chain test vehicle was used to demonstrate this technology as a first proof of concept. Full transition to Cu6Sn5 was successfully achieved within a minute at 260°C as confirmed by scanning electron microscope (SEM) and x-ray energy dispersive spectroscopy (XEDS) analysis. The joint composition was stable through 10× reflow, with outstanding bond strength averaging 90 MPa. The metastable SLID interconnections also showed excellent electromigration performance, surviving 500 h of current stressing at 105 A/cm2 at 150°C.

Reliability Studies of 5 µm Diameter Photo Vias with Daisy Chain Resistance Using Dry Film Photosensitive Dielectric Material

Abstract: This paper will demonstrate reliability of via diameter below 5 µm using panel-scalable dry film photosensitive dielectric. The dielectric used is IF4600 series, an epoxy based dry film photosensitive dielectric. The test vehicle comprising of daisy chain of microvias was patterned using semi-additive process. A novel dry film photoresist was used for patterning the daisy chain structure. Thermal cycling reliability studies will be performed to detect any failures in the microvia structures. The scaling down of microvias below 5 µm diameters with dry film photosensitive dielectrics will enable high density redistribution layer (RDL) technology for panel-based fan-out and interposer substrates.

Glass in Electronic Packaging and Integration: High Q Inductances for 2.35 GHz Impedance Matching in 0.05 mm Thin Glass Substrates

Abstract: This work demonstrates 50 µm (2.0 mil) thin SCHOTT glass AF32eco as a RF substrate. Superior electrical performance and miniaturized component or package size in both vertical and lateral dimensions compared to traditional components and two-dimensional (2D) packages are shown to be feasible with the 3D fabrication approach with such thin glass. Vias with a diameter of 50µm are made at SCHOTT using laser structuring. Either sides of the glass substrates are coated with a thin layer of a polymer dielectric. The through-holes are re-opened and metallization processes are performed to simultaneously create a thick copper metallization on both surfaces as well as on the vias to make them conducting. The metallization is structured with semi-additive patterning using photolithography and etching to obtain solenoid inductors for matching networks of filter elements. The magnetic field of the components is mainly parallel to the glass substrate. Inductances with 1.7 nH and 1.9 nH are designed and fabricated using different structures for shielding. The performance metrics of the demonstrated glass-integrated passive devices (IPDs) and modules were characterized. Excellent correlation between modeling and measured results were observed. Characterization of the inductances revealed quality factors (Q-values) of 60 and more at 2.35 GHz. The Q-values of the inductances are confirmed by three independent measurement methods and correspond well to field simulation results. The basic building blocks demonstrated in this paper can lead to a new generation of ultra-thin 3D RF modules with substrate-embedded matching networks and filters, superior performance and lower cost compared to laminate and FO-WLP based approaches.

Design and demonstration of ultra-thin 3D glass-based 5G modules with low-loss interconnects

Abstract: This paper demonstrates six-metal-layer antenna-to-receiver signal transitions on panel-scale processed ultra-thin glass-based 5G module substrates with 50-Ω transmission lines and micro-via transitions in re-distribution layers. The glass modules consist of low-loss dielectric thin-films laminated on 100-μm glass cores. Modeling, design, fabrication, and characterization of the multilayered signal interconnects were performed at 28-GHz band. The surface planarity and dimensional stability of glass substrates enabled the fabrication of highly-controlled signal traces with tolerances of 2% inside the re-distribution layers on low-loss dielectric build-up thin-films. The fabricated transmission lines showed 0.435 dB loss with 4.19 mm length, while microvias in low-loss dielectric thin-films showed 0.034 dB/microvia. The superiority of glass substrates enable low-loss link budget with high precision from chip to antenna for 5G communications.

Design and Analysis of Receiver Channels of Glass Interposers for 5G Small Cell Front End Module

Abstract: In this paper, we design and analyze receiver channels of a glass interposer for a 5G small cell front end module (FEM). In RF systems, a 50 ohm impedance matching is important for RF channels to guarantee the target RF sensitivity of the RF system. Receiver channels of glass interposers for the 5G small cell FEM are designed, analyzed and characterized up to 40 GHz considering the impedance matching. Using the designed receiver channels, the glass interposer based the 5G small cell FEM is designed and analyzed up to 40 GHz.