Showing papers by "Rao Tummala published in 2019"

Advanced Low-Loss and High-Density Photosensitive Dielectric Material for RF/Millimeter-Wave Applications

Abstract: Electrically low-loss and high-density interconnection between components in a package have been one of the most critical metrics for next-generation 5G millimeterwave packages. This paper describes an innovative low-loss photosensitive dielectric material, which enables sub- $10\ \mu \mathrm{m}$ photo-patterning and shows low dissipation factor, known as Df. Dielectric properties providing low-loss interconnects were characterized by ring-resonator method. The results showed a dielectric constant (Dk) of 2.8 and a dissipation factor (Df) of less than 0.005 up to 40 GHz. This material is also designed to have a comparatively low curing temperature of 200°C, high elongation >50%, and high adhesion, and low surface roughness. This paper also presents the demonstration of low-loss and high-density signal routings using dual damascene process with the material. The innovative photosensitive dielectric material, reported in this paper, is a promising candidate to enable high-performance, high-density fan-out and interposers for RF and 5G mm-wave applications.

Fabrication and Reliability Demonstration of 3 µm Diameter Photo Vias at 15 µm Pitch in Thin Photosensitive Dielectric Dry Film for 2.5 D Glass Interposer Applications

Abstract: In this paper, the authors report on the development of a novel epoxy-based photosensitive dielectric dry film material (PDM). The PDM has two key features: 1) Low CTE value of 30 ppm/°C resulting from the concentration optimization of nano-sized fillers in the material composition, 2) Low Stress of the PDM films, attributed to low-temperature (180 °C) processing of the polymer dielectric which is lower than most of the known advanced dielectric materials. Improvements reported on these two key features will significantly enhance the reliability of high-density packages. To assess the reliability of the PDM, we have fabricated a high-density daisy chain structure on the glass panel consisting of 400 vias of 3 µm diameter at 15 µm pitch. We have also used the PDM as passivation layer on the surface of the test vehicle. Following the fabrication of the test microvia chain, electro-less nickel immersion gold (ENIG) process was performed for surface finish. We have performed reliability measurements of the 3 µm diameter vias after nHAST (Non-Bias Highly Accelerated Stress Tests) at 130 °C, 85 % R.H. for 100 hours followed by thermal cycling test (TCT) with a dwell time of 15 minutes at 125 °C and -55 °C. We have observed no open circuit failure occurred during the TCT. We measured the resistance of the daisy chain circuit by four-point probe method every 100 cycles up to a total of 1500 cycles. The resistance change was less than 5 % even after 1500 cycles which clearly demonstrate the superior reliability of the PDMs. In conclusion, the newly developed PDM is a suitable dielectric material for high-density RDL applications such as 2.5D interposers and fan-out packages.

Innovative Sub-5- $\mu$ m Microvias by Picosecond UV Laser for Post-Moore Packaging Interconnects

Abstract: This article presents for the first time microvias scaled down to sub- $5~\mu \text{m}$ in diameter fabricated using picosecond UV laser ablation in a nonphotoimageable dielectric film. The motivation of this article is to address post-Moore and More-than-Moore packaging interconnect needs. Microvias play a critical role in package interconnections in IO density and the IC bump pitch for 2.5-D interposers and fan-out packages. UV laser ablation has been the key technology for fabricating small microvias in high density interconnect (HDI) packaging for more than two decades. The state-of-the-art microvia fabricated by UV laser ablation is still at $20~\mu \text{m}$ in diameter and 50 $\mu \text{m}$ in pitch. This article explores the feasibility of fabricating microvias of $5~\mu \text{m}$ or less in diameter with a commercially available picosecond UV laser system. The experimental results show that microvias of $5~\mu \text{m}$ or less in diameter in a 5- $\mu \text{m}$ -thick Ajinomoto buildup dielectric film (ABF) are achieved. This article also addresses the fundamentals of picosecond pulsed laser ablation on polymer dielectric materials and processes optimization to generate sub-5- $\mu \text{m}$ microvias. The via pitch of 8– $12~\mu \text{m}$ is demonstrated. UV laser ablation also addresses the issue of limited availability of photosensitive dielectric materials for photolithography-based microvia fabrication.

Low-Cost Non-TSV Based 3D Packaging Using Glass Panel Embedding (GPE) for Power-Efficient, High-Bandwidth Heterogeneous Integration

Abstract: This paper demonstrates a next-generation non-TSV 3D packaging architecture with small form-factors, excellent electrical performance and reliability at low cost for high-bandwidth applications. High density Logic-HBM integration, today, is built predominantly using 2.5D interposers which are fundamentally limited by long interconnect lengths, and they also are expensive as the package sizes increase. Although 3D ICs enable lowest possible latencies and power-efficiencies, they are challenged by power-delivery and thermal management issues. This paper presents, for the first time, a non-TSV based 3D architecture using Glass Panel Embedding (GPE) technology for high-density large package applications achieving excellent bandwidth and power-efficiency that are not possible in current approaches. The tailorable CTE of glass allows a reliable direct board SMT of large GPE packages that not only benefits form factor and signal speed, but also provides radical benefits to power delivery. This paper also studies the fundamental limitations of fan-out structures like warpage that limit today's mold-based fan-out packages, and through process improvements achieve <80 µm across 100x100 mm panel enabling HBM assembly at 40 µm pitch.

Innovative Socketable and Surface-Mountable BGA Interconnections

Abstract: This paper introduces a universal BGA technology that can reliably be used both in sockets and SMT applications. Socketing and SMT have been driving two different board-level interconnection technologies: LGA for socketing, to provide a stable and reworkable mechanical contact, and BGA for SMT, for low-temperature metallurgical bonding to the board. Enabling socketable BGAs has become critical to simplify microprocessor package designs and converge towards a unique product. The approach presented in this research involves the use of multi-layered coatings on solder spheres. These coatings consist of a diffusion barrier/noble metal combination designed based on diffusion models to meet the requirements of both applications. Standard surface finish Electroless Ni Immersion Au (ENIG) has been studied in detail as a first approach. This paper focuses on the challenges faced in plating ENIG on traditional SAC solder balls and a new process combining sputtering and electrodeposition is demonstrated as a promising alternative to uniformly coat solder spheres with a controlled thickness of ENIG without corrosion. A first demonstration of attaching these coated spheres to the package is also presented.

Next Generation of 2-7 Micron Ultra-Small Microvias for 2.5D Panel Redistribution Layer by Using Laser and Photolithography Technologies

Abstract: Microvia is the vertical interconnect structure for multi-layer redistribution layers (RDLs) in high-density interconnect (HDI) printed circuit boards (PCBs), HDI package substrates, 2.5D interposers and fan-out packages. Three technologies such as photolithography, UV laser and excimer laser have been used to form small microvias (≤ 20 µm diameter) in polymer dielectrics. All the three above mentioned technologies are studied and compared in the work presented in this paper. Photovia was first introduced by IBM for Surface Laminar Circuit technology and it has scaled down from 125 µm then to below 10 µm today. The smallest photovia demonstrated is 2 µm in diameter by using 365 nm photolithography in 5 µm thick TOK photo-imageable dielectric (PID) (IF4605) film. Photovias of 3 µm diameter were also demonstrated in 5 µm thick Taiyo Ink dielectric dry film material (PDM) which passed 1,500 thermal cycles (-55 C to 125 C). The limitation of photovia technology is the availability and cost of photo-sensitive dielectric materials with the required electrical, mechanical, thermal and chemical properties. The state-of-the-art microvia diameter is 20 µm by using conventional high-speed UV laser technologies. Multi-layer RDL with microvias and trenches of 4 µm feature sizes are simultaneously fabricated in a 7 µm thick Ajinomoto Build-up Film (ABF) with small fillers by using excimer laser and passed 1,000 thermal cycles (-55 C to 125 C). This paper demonstrates a novel picosecond UV laser technology to push the limits of low-cost UV laser technology by optimizing laser parameters and dielectric materials. The Cornerstone picosecond UV laser tool from ESI is capable of producing output power of 16W at 355 nm wavelength. The pulse duration is 5 ps which minimizes the heat-affected zone of polymer dielectric and the high (80 MHz) repetition rate enables this laser to be used in high throughput manufacturing processes. Microvias with minimum diameter of < 7 µm were fabricated in 5 µm thick ABF with small fillers and in 7 µm thick novel Panasonic low stress dielectric film-S (PLS-S), by using 355 nm picosecond UV laser tool. These ABF and PLS-S films are non-photosensitive dielectric materials. This is the first demonstration of very small microvias (< 7 µm) in polymer dielectrics using UV laser ablation. The motivation of this work is to address the high RDL interconnect density requirements for 2.5D interposer and high density (HD) fan-out packages. The next generation of low-cost, ultra-small microvias will (1) Increase the RDL I/O density, (2) Meet fine bump pitch requirements, (3) Reduce the metal layer count for package substrate RDL, (4) Fill the gap between semiconductor back-end-of-line (BEOL) process and semi-additive process (SAP) and thereby (5) Improve the packaging performance at lower costs.

Evaluation of Fine-Pitch Routing Capabilities of Advanced Dielectric Materials for High Speed Panel-RDL in 2.5D Interposer and Fan-Out Packages

Abstract: High-bandwidth computing with low power requires high-density low-loss interconnects with advanced design rules that cannot be realized with standard epoxies. This paper evaluates the critical material properties required to meet nextgeneration RDL needs for 2.5D interposer and fan-out packages. It demonstrates that shifting towards lower Dk materials can support higher data rates and maintain high wiring density, thus enabling overall system bandwidth improvement. This paper provides a complete analysis of the material property requirements, critical design metrics, and process options to qualify dielectrics for next-generation highbandwidth demand.

3D Glass Package-Integrated, High-Performance Power Dividing Networks for 5G Broadband Antennas

Abstract: This paper demonstrates package-integrated power dividers with footprint smaller than the free-space wavelength corresponding to the operating frequency of 28 GHz band for 5G Antenna-in-Package (AiP), by utilizing precision low-loss redistribution layers (RDL) on glass substrates for highly-integrated mixed-signal systems. Two configurations of power dividers with two-way and three-way equal power split are modeled, designed and fabricated on glass substrates with thin-film build-up layers. This approach combines the benefits of ceramic and low-loss polymers for electrical performance, and silicon-like dimensional stability of glass for precision panel-scale patterning. Multilayered RDL with sub-20 micron features are utilized to design innovative power divider topologies with benefits in terms of low added insertion loss (<0.8-dB) and minimal phase-shift between the output ports, due to high precision of distributed transmission lines and through panel vias (TPVs). These power dividing networks depict upto 25% lower added insertion loss as compared to similar structures on fine pitch InFO RDL. The power dividers are also configured as 2×1 and 3×1 antenna arrays using Yagi-Uda antennas which cover the entire 28 GHz 5G band. The performance of power dividers as well as corresponding antenna arrays shows an excellent correlation between simulated and measured results.

Laser-drilling formation of through-glass-via (TGV) on polymer-laminated glass

Abstract: A three-dimensional (3D) glass integrated passive device (IPD) is an evolutionally advanced configuration to dramatically reduce the electronics form factor and manufacturing cost of current IPDs by introducing ultra-thin glass with through-glass-vias (TGVs). A defect-free TGV formation technology in polymer-laminated glass substrates is required to realize a highly reliable 3D glass IPD. This paper discusses mechanisms of each defect formation in the use of several types of lasers to explore suitable technology for defect-free drilling in polymer-laminated glass.

Low-Cost 1- $\mu$ m Photolithography Technologies for Large-Body-Size, Low-Resistance Panel-Based RDL

Abstract: This paper presents the latest advances in photolithography technologies to enable scaling of package redistribution layer (RDL) toward critical dimensions (CD) of $1 ~\mu \text{m}$ and below. High-bandwidth memory channels require not only fine pitch but also low-trace-delay RDL. High-aspect-ratio (AR) traces enable lower delays, and the photolithographic advances to achieve such traces are demonstrated on panel-based glass substrates for packages with low cost, high input/output (I/O) density, high bandwidth, and large body size. CD of 0.9- $\mu \text{m}$ line and space with an AR of 5.5 was successfully demonstrated using a low-numerical aperture (NA = 0.16) $1 \times$ i-line projection stepper tool with a novel chemically amplified plating photoresist. The 1- $\mu \text{m}$ lithography technology is a must for high-density RDL to enable 2.5-D interposer and embedded fan-out package substrates. These architectures can achieve I/O densities of 500 IOs/mm/layer. The resistance of the trace with an AR of 5 is five times lower than a trace with an AR of 1. This technological advance will greatly reduce the signal propagation loss and increase the data rate of the RDL traces. The combination of high density and high data rate will greatly increase the system interconnect bandwidth. Furthermore, low-NA stepper with a large exposure area will enable the fabrication of large-body-size interposers at low cost. This paper analyzes the relationship between trace width resolution ( $w$ ), depth of focus, and materials to conclude that it is feasible to fill the gap between semiconductor back-end-of-line and package substrate RDL technologies. The final section discusses the issues in process development of lithography for multilayer fine-line RDLs.

Low-Loss Additively-Deposited Ultra-Short Copper-Paste Interconnections in 3D Antenna-Integrated Packages for 5G and IoT Applications

Abstract: High-bandwidth 5G and 6G communication systems will inevitably migrate to 3D package architectures with backside or embedded dies and antenna-integrated packages for ultra-low losses and smaller footprints. With the trend to such 3D millimeter-wave (mm-wave) packages, the losses from the assembly and through-vias tend to dominate the overall losses. Traditional wirebond and thick solder interconnections lead to large mm-wave interconnect losses that are not acceptable for emerging 5G and 6G communications. This paper focuses on the material syntheses and process development of nanocopper interconnections with ultra-low interconnect losses for chip-last or flip-chip assembly in packages. The first part of the paper introduces the material synthesis of an innovative copper paste with shorter sintering times and temperatures. Optimized conditions are obtained to attain a conductivity of 1.4x10^7 S/m. This is equivalent to 82% increase in conductivity compared to that of solder. The surface roughness is also measured through atomic-force microscopy. Results suggest that the copper paste features higher roughness than that of solders. The second part of this paper discusses the potential of novel nanocopper paste to replace solders as a package assembly material, focusing on the effect of the conductivity and surface roughness with regard to the insertion loss in interconnection bumps. Based on the improved material properties of nanocopper paste, the model shows a 53% reduction in the dB scale at 28 GHz, by employing nanocopper paste. Die shear test for copper paste is also performed to show a high potential to replace solders as a flip-chip assembly material in both printed-circuit-board and mm-wave packaging technologies.

In-Situ Investigation of Organic Additive Interactions in Copper Electroplating Solutions with Surface Enhanced Raman Spectroscopy (SERS)

Abstract: To meet demand for increasingly higher-performance electronics in increasingly smaller form factors, achieving higher logic-memory bandwidth and higher I/O density is required. This necessitates finer copper lines, smaller copper microvias, and fine-pitch, copper-filled through-package vias (TPVs). However, low-quality copper filling in highaspect ratio TPVs can lead to void formation and mechanical failures. This poses various material and process challenges for the achievement of high-quality copper metallization. These challenges can be addressed through a better understanding of copper deposition mechanisms and investigating the fundamental aspects of copper plating chemistry. In this study, in-situ interactions between different classes of organic additives in copper plating solutions were investigated with surface-enhanced Raman spectroscopy (SERS). A novel test set up is developed which allows for the direct observation of copper plating within a via. SERS was used to observe cases of competitive adsorption between suppressor, leveler, and accelerator additives within this ’via’. These observations are used to infer the impact of different classes of additives on viafilling performance and correlate the electrochemical behavior in the plating cell. A model is proposed to explain the relative tendencies of the differing classes of additives to adsorb to the copper surface within a via.

3-D Packaging and Integration of High-Density Tantalum Capacitors on Silicon

Abstract: High-density, point-of-load (PoL) power conversion and power delivery are required to continue scaling electronic systems with increased functionality, more bandwidth, and smaller sizes. To meet the demands of these highly complex and miniaturized electronic systems, new 3-D integration schemes of advanced passive and active components are needed to enable the next-generation power distribution networks (PDNs). In addition, shorter interconnect lengths are required to provide low losses and better transient response in switch-based power conversion systems. Tantalum capacitors have the potential to provide some of the highest volumetric densities of any current capacitor technology, but are generally bulky components with low frequency stability, limiting their use in future 3-D power systems. In this paper, a process for the embedding and integration of ultrathin, high-density tantalum capacitors with improved frequency stability is demonstrated. The 5-V capacitors show a density of $1~\mu \text{F}$ /mm2 at 1 MHz with only a 100- $\mu \text{m}$ thickness, and are shown to be capable of direct integration on silicon for short interconnect length of $ . The electrical performance of the capacitors is tested after integration and shows that they retain high capacitance density and low equivalent series resistance (ESR), while also providing low leakage currents. The combination of low loss, high volumetric density, and 3-D integration capability make the capacitors an ideal candidate for next-generation power modules.

Design and Demonstration of 1µm Low Resistance RDL Using Panel Scale Processes for High Performance Computing Applications

Abstract: This paper presents for the first time the latest challenges and solutions to enable electronics packaging redistribution layer (RDL) scaling to 1µm and beyond. The focus on RDL scaling for this paper is on how to scale semi-additive processing (SAP) for next generation high performance computing applications such as 2.5D Interposers. This paper combines novel next generation photoresist materials developed by Tokyo Ohka Kogyo Co., LTD. (TOK) and process innovations to the traditional SAP process. Traditionally, challenges in scaling SAP are related to seed layer etching and photoresist materials selection. This paper address both of these challenges by exploring various seed layer metals and the potential impact they can have on the SAP process flow for enabling SAP scalability as well as novel photoresist development with TOK. Scaling dry films to have similar performance to a matching liquid photoresist is demonstrated in this paper. The 3D Systems Packaging Research Center remains one of the leaders in package RDL scaling and this paper discusses at length recent advancements that have been made to enable silicon like RDL scaling on glass panels.

First Demonstration of Ultra-Thin Glass Panel Embedded (GPE) Package with Sheet Type Epoxy Molding Compound for 5G/mm-wave Applications

Abstract: With the number of connected-devices increasing tremendously, communication data rates are projected to be at least 10–100X in the 5G/mm-wave (MMW) technology - much higher than the existi...

Ultra-Wideband, Glass Package-Integrated Power Dividers for 5G and mm-Wave Applications

Abstract: This paper presents an ultra-wideband, glass package-integrated, equal-split power divider with footprint smaller than the unit free-space wavelength corresponding to the operating frequency of 28 GHz 5G band. The utilization of precision low-loss redistribution layers (RDL) on ultra-thin glass substrates with stable electrical properties at mm-wave frequencies enable the ultra-wideband power dividing networks to have a small footprint in x-y-z dimensions along with excellent performance. This approach aggregates the benefits of ceramic, low-loss polymers and silicon: electrical performance of the ceramic, processability of polymers and the dimensional stability of silicon, simulated in glass substrate to realize fine features for the power dividers. The power divider exhibits low added insertion loss, minimal phase shift between its output ports and has a height less than 150-µm.

3D Glass-Based Panel-Level Package with Antenna and Low-Loss Interconnects for Millimeter-Wave 5G Applications

Abstract: This paper reports the first demonstration of antenna-in-package and seamless antenna-to-receiver signal transitions on panel-scale processed ultra-thin glass substrates, for high-speed 5G communication standards in the 28 GHz band. To demonstrate the benefits of g 1 ass for 5 G communications, package-integrated antennas with feedlines were modeled and designed on ultra-thin glass substrates laminated with low-loss dielectric thin films for highest bandwidth and efficiency in the mm-wave bands. The measured results for a miniaturized Yagi-Uda antenna, transmission lines, and through-package vias showed superior dimensional stability and good agreement with the simulated values on 100 µm glass substrates. The results showed low interconnect signal losses with a microstrip line loss of 0.108 dB/mm, and a through-package via loss of 0.095 dB/TPV. The Yagi-Uda antenna fabricated on glass substrates showed a center frequency of 28.18 GHz with a fractional bandwidth of 21.1%. The antenna also presented a wide-angle main lobe at the target frequency range implying good coverage of signal transmitting and receiving. The performance of package-integrated antenna, feedlines, through-package vias, and transmission lines on glass substrates was benchmarked in comparison to other 5G substrate technologies such as organic laminate, ceramic-based substrates, or fan-out wafer level packaging.

Design and Measurement of a 28 GHz Glass Band Pass Filter based on Glass Interposers for 5G Applications

Abstract: In this paper, we design and measure 28 GHz band pass filter (BPF) based on glass interposer for 5G applications. We design the parallel coupled resonator BPF based on the glass interposer. To control the even- and odd mode characteristic impedance, we adopt the multi-layer ground. Also, to reduce the channel loss, the wide coupled channels for 28 GHz BPF are designed. Designed 28 GHz glass BPF was verified by simulation using the 3D-EM simulator. Also, Designed 28 GHz glass BPF was fabricated to verify the electrical performance through measurement. Simulated and measured insertion loss of the designed 28 GHz glass BPF is −2.4 dB and −3.4 dB at 28 GHz, respectively.

Cu Pillar with Nanocopper Caps: The Next Interconnection Node Beyond Traditional Cu Pillar

Abstract: Off-chip interconnection pitch scaling has been aggressively driven over the last several decades by the continuous need for higher bandwidth and computing power in smaller form factors in emerging high-performance computing systems. It is expected to reach below 10µm I/O pitch in the near future, beyond the fundamental limits of traditional solder-based interconnection technologies. While the Cu pillar with solder caps technology remains attractive in chip-to-substrate (C2S) applications as it can accommodate substrate and chip non-coplanarities during assembly through melting of the solder, all-Cu interconnections are now pursued as the next interconnection node for their pitch and performance scalability. However, direct Cu-Cu bonding faces several key challenges that have hindered large-scale adoption in C2S, including its relatively high elastic modulus, giving low compliance in assembly. To address this challenge, a novel interconnection technology - Cu pillar with nanocopper caps - is proposed where a solid-state sub-20 GPa modulus nanoporous Cu cap is introduced to replace the solder cap and retain solder-like compliance in assembly, while achieving bulk-like properties through densification in low-temperature sintering. This paper presents the design of this new interconnection system, the developed wafer bumping process, compatible with current industry infrastructures, and a first assembly demonstration where a seamless interface was achieved.

3D Packaging with Embedded High-Power-Density Passives for Integrated Voltage Regulators

Abstract: Highly-integrated 3D voltage regulators (IVRs) for high-power applications are developed for emerging applications such as AI computing and server. With this 3D process integration, passive components such as inductors and capacitors are embedded into substrates and placed close to the chips, resulting in short power delivery networks (PNDs) and high power efficiency. High-density tantalum capacitors are integrated with high-density magnetic-core inductors to realize IVRs with module thickness around 0.7 mm. By incorporating high-permeability magnetic materials as the cores, the inductors achieved 20X improvement in inductance as compared to air-core inductors. The high inductance allows inductors to be designed with less number of windings, resulting in low component resistance of 5 mΩ. The integrated components have package-compatible terminals that are compatible with electrolytic plating process. The terminals allow them to be connected with low-resistance vias to further reduce parasitic losses and improve the power efficiency. Short PDNs and low-resistance interconnections and low-resistance components make the demonstrated IVRs ideal for high-power density computing applications with high efficiency low-impedance power delivery networks.

Solder paste wicking in socketable BGAs

Abstract: The trend of the electronics industry to miniaturize package design has caused the need to adopt BGA packages for a variety of applications. OEM microprocessors have conventionally used LGA designs...

Substrate-compatible inductors with magnetic layers

Abstract: An exemplary embodiment of the present invention provides a planar inductor comprising a substrate, a first magnetic layer, a conductive coil, and a second magnetic layer. The first magnetic layer can be disposed on at least a portion of the substrate. The conductive coil can be disposed on a first portion of the first magnetic layer. The second magnetic layer can be disposed on a second portion of the first magnetic layer and on at least a portion of the conductive coil.