Rao Tummala

TL;DR: In this article, the authors summarized the historical evolution of microvia technologies worldwide and discussed the key emerging global microvia research and development in the fabrication of multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 /spl mu/m and low-cost stacked via structures without chemical-mechanical polishing.

TL;DR: In this paper, a package integration of 5G filters with ultrashort 3D interconnects allows for low interconnect losses that are similar to that of on-chip filters, but low component insertion loss of off-chip discrete filters.

TL;DR: In this article, the authors compared the thermal performance of glass and silicon interposers for mobile applications, using computational modeling, and showed that glass interposer provides significantly better thermal isolation between logic and memory chips.

TL;DR: In this paper, a numerical and experimental analysis of thermomechanical deformation in high-aspect-ratio copper electroplated through-silicon vias (TSVs), which were fabricated by deep reactive ion etching, thermal oxidation, and bottom-up electroplating processes, is presented.

TL;DR: In this article, the first time such high Q inductors have been demonstrated in this technology, the different inductor designs, optimization schemes, and trade-offs between different topologies have been discussed.