Rao Tummala

Bio: Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.

Low-cost and low-loss 3D silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC

Abstract: This paper presents the design, fabrication and electrical characterization of a low loss and low cost non-traditional silicon interposer, demonstrating the high bandwidth chip-to-chip interconnection capability of the 3D silicon interposer, with equivalent or better performance than 3D ICs with TSVs, at a much lower cost. This scalable approach uses thin polycrystalline silicon in wafer or panel form, forms lower cost through-package-vias (TPVs) at fine pitch by special high throughput laser processes. The electrical performance is improved by thick polymer liners within the TPVs. Double side package processes for TPV metallization and RDL layers using dry film polymers and plating leads to significant cost reduction compared to single side TSV and BEOL wafer processes. Combined loss of 3mm long CPW lines and two TPVs in the low loss silicon interposer was demonstrated at less than 1dB at 10GHz. The fine pitch TPV capability and low loss of this non-traditional silicon interposer leads to 3D interposers with double side chips interconnected at equivalent bandwidth to wide bus I/O 3D ICs at a much lower cost and with better testability, thermal management and scalability.

Chip-to-chip optoelectronics SOP on organic boards or packages

Abstract: In this paper, we demonstrate compatibility of hybrid, large-scale integration of both active and passive devices and components onto standard printed wiring boards in order to address mixed signal system-on-package (SOP)-based systems and applications. Fabrication, integration and characterization of high density passive components are presented, which includes the first time fabrication on FR-4 boards of a polymer buffer layer with nano scale local smoothness, blazed polymer surface relief gratings recorded by incoherent illumination, arrays of polymer micro lenses, and embedded bare die commercial p-i-n photodetectors. These embedded optical components are the essential building blocks toward a highly integrated SOP technology. The effort in this research demonstrates the potential for merging high-performance optical functions with traditional digital and radio frequency (RF) electronics onto large area and low-cost manufacturing methodologies for multifunction applications.

SiC-shell nanostructures fabricated by replicating ZnO nano-objects: a technique for producing hollow nanostructures of desired shape.

Abstract: Hollow nanostructures have important applications due to their large outer and inner surfaces, as well as cavity-confined nanoscale reactions and transport processes. The simplest hollow structures are nanoparticle and nanotubes shells. Compared to solid nanoparticles or nanorods and nanowires, tubular nanostructures of inorganic materials have potential applications in biotechnology, such as drug delivery, gene delivery, gene therapy, biosensors, and bioanalysis and catalysis. In addition, when the tubular structures are filled with special biomolecules, the structures may act as delivery channels for such molecules. The tubular structures are made either by direct growth or by nanowire-templated epitaxial growth using metal-organic chemical vapour deposition (MOCVD). Here, we extend the template-assisted method for fabricating shelled structures of nano-objects of desired shapes and configurations. Our technique is based on replicating ZnO-based nanostructures by SiC at low temperatures. Subsequent dissolution of ZnO leaves a SiC shell that preserves the same shape as the original ZnO nanostructure. The SiC hollow nanostructures could be used as nanoreactors, molecular transporters, and more. The methodology demonstrated here can be extended to other types of shelled structures of different chemical compositions. Silicon carbide is an important semiconductor in the fabrication of electronic devices operated at high temperature, power, and frequency and in harsh environments. Several groups have reported the fabrication of one-dimensional (1D) SiC nanotubes using template-assisted growth methods at high temperatures. [10–12] Borowiak-Palen et al. produced SiC nanotubes based on high-temperature (1350 8C) reactions between silicon powders and multi-walled carbon nanotubes. Hu et al. formed SiC nanotubes by reacting CH4 with SiO at 800 8C. Sun et al. prepared SiC nanotubes by reacting SiO with carbon nanotubes at 1250 8C. However, the high growth temperature limits the integration of the current growth method with semiconductor fabrication technology, which usually requires growth temperatures below 500 8C. In recent years, our group has done much research on the growth of various ZnO nanostructures using a vapor– solid growth process. Figure 1 shows the morphologies of selected ZnO nanostructures that were used as templates in the following experiments for fabricating SiC hollow structures. The nanobelts shown in Figure 1a have a uniform shape along their growth axis. Figure 1b shows the morphology of tin-catalyzed ZnO nanowires. The ZnO nanowires typically have a large tin catalyst at their tips (as shown in the left-hand inset of Figure 1b). The tin catalyst is much larger than the nanowire. In some cases, two ZnO nanowires share a single catalyst particle (right-hand inset of Figure 1b). Figure 1c–e shows the scanning electron microscopy (SEM) images of various ZnO nanostructures (combs, junctions, and helices, respectively). The synthesis strategy of the SiC hollow nanostructures involved two steps, as shown in Figure 2. Firstly a SiC layer was deposited on the surface of the ZnO nanostructure templates to form ZnO–SiC core–shell nanostructures via plasma-enhanced chemical vapor deposition (PECVD). The source materials for SiC were CH4 and SH4 gases, and the deposition temperature was 250–300 8C. Secondly, the ZnO–SiC core–shell nanostructures were added to a dilute HCl solution ( 0.2 molL ) to remove the ZnO cores. Finally, only SiC tubelike nanostructures were left, retaining the corresponding shapes of the ZnO nanostructure templates. Transmission electron microscopy (TEM) was used to reveal the shell structure of the replicated nanostructures. Figure 3a shows a typical TEM image of the ZnO–SiC core–shell nanobelt synthesized in this work. The ZnO nanobelt coated with a uniform SiC shell is clearly indicated based on the contrast of the TEM image. The shell along the ZnO nanobelt is uniform and smooth. In our experiments, the thickness of the layer can be tuned by adjusting the parameters in the PECVD process. Energy dispersive X-ray (EDX) analysis (inset of Figure 3a) revealed that the core–shell nanobelt is composed of Zn, O, Si, and C. No other elements were found, indicating that the shell on the [*] J. Zhou, J. Liu, R. S. Yang, C. S. Lao, Dr. P. X. Gao, Prof. Z. L. Wang School of Materials Science and Engineering Georgia Institute of Technology Atlanta, GA 30332-0245 (USA) Fax: (+1)404-894-9140 E-mail: zhong.wang@mse.gatech.edu

Liquid crystal polymers (LCP) for high performance SOP applications

Abstract: Electronic devices will increasingly rely on new materials with improved properties such as lower coefficient of thermal expansion preferably close to silicon, higher modulus, lower permittivity & loss, lower moisture absorption, better thermal conductivity, good dimensional stability, and more importantly reduced warpage particularly after the build-up process. The thermal properties of LCP's have led to increasing interest for the packaging community. This work deals with the evaluation of LCP's for future electronic packaging applications. LCP samples obtained from industry were analyzed using TA instruments. The samples with the properties best matched to the needs of future electronic packaging applications will be chosen based on the thermal analysis data presented for (i) fabrication of a base substrate using solely reinforced LCP, (ii) evaluating LCP for use as a carrier film, (iii) performing laser ablation techniques for via formation in the build up layers, and (iv) plating of the vias and the films for through hole Z-direction connections and X, Y, signal lines. In the present work, application of LCP as a dielectric layer for the system-on-package process has been evaluated. It is expected that the reinforced LCP films can also be utilized as a substrate material thereby providing the unique opportunity for superior compatibility between the substrate and the dielectric layer.

Reliability assessment of microvias in HDI printed circuit boards

Abstract: Accelerating adoption of CSP and flip-chip area array packaging for high performance and hand-held applications is the main driving force for high-density substrates and printed circuit boards. At the Packaging Research Center, Georgia Institute of Technology (PRC-GT), ultra-fine line high density interconnect (HDI) substrate technology is being developed as part of the system-on-a-package (SOP) research and testbed efforts to meet these emerging requirements. To be adopted by industry, this novel technology must demonstrate the critical elements of high reliability and low cost processing. The HDI and microvias structures discussed in this paper were fabricated on high Tg organic substrates using a sequential build-up process, and were subject to extensive liquid to liquid thermal shock testing. All 75 /spl mu/m microvias and above successfully passed 2000 cycles without failure, and first failure occurred at 1000 cycles for 50 /spl mu/m microvias on a 50 /spl mu/m thick dielectric layer. Microvia down to 25 /spl mu/m diameter on a 25 /spl mu/m thick dielectric layer have passed 2000 cycles with zero failures. Cross-sectioning confirmed that failures were caused by process related defects, such as thin electrolytic copper plating. This paper will discuss the reliability results of the PRC HDI microvias process and methods to improve the mechanical reliability of small photo defined microvias fabricated on similar laminate substrates.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Microfibre–nanowire hybrid structure for energy scavenging

Abstract: Nanodevices don't use much energy, and if the little they do need can be scavenged from vibrations associated with foot steps, heart beats, noises and air flow, a whole range of applications in personal electronics, sensing and defence technologies opens up. Energy gathering of that type requires a technology that works at low frequency range (below 10 Hz), ideally based on soft, flexible materials. A group working at Georgia Institute of Technology has now come up with a system that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing their associated nanowires together, mechanical energy is converted into electricity via a coupled piezoelectric-semiconductor process. This work shows a potential method for creating fabrics which scavenge energy from light winds and body movement. A self-powering nanosystem that harvests its operating energy from the environment is an attractive proposition for sensing, personal electronics and defence technologies1. This is in principle feasible for nanodevices owing to their extremely low power consumption2,3,4,5. Solar, thermal and mechanical (wind, friction, body movement) energies are common and may be scavenged from the environment, but the type of energy source to be chosen has to be decided on the basis of specific applications. Military sensing/surveillance node placement, for example, may involve difficult-to-reach locations, may need to be hidden, and may be in environments that are dusty, rainy, dark and/or in deep forest. In a moving vehicle or aeroplane, harvesting energy from a rotating tyre or wind blowing on the body is a possible choice to power wireless devices implanted in the surface of the vehicle. Nanowire nanogenerators built on hard substrates were demonstrated for harvesting local mechanical energy produced by high-frequency ultrasonic waves6,7. To harvest the energy from vibration or disturbance originating from footsteps, heartbeats, ambient noise and air flow, it is important to explore innovative technologies that work at low frequencies (such as <10 Hz) and that are based on flexible soft materials. Here we present a simple, low-cost approach that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing the nanowires rooted on them with respect to each other, mechanical energy is converted into electricity owing to a coupled piezoelectric–semiconductor process8,9. This work establishes a methodology for scavenging light-wind energy and body-movement energy using fabrics.

Self-powered nanowire devices.

Abstract: The lateral and vertical integration of ZnO piezoelectric nanowires allows for voltage and power outputs sufficient to power nanowire-based sensors.