Rao Tummala

Bio: Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.

“zero-undercut” semi-additive copper patterning - a breakthrough for ultrafine-line RDL lithographic structures and precision RF thinfilm passives

Abstract: This paper presents the first demonstration of a “zero-undercut” precision formation of ultrafine-line copper conductor patterns for redistribution layers (RDL) and thin film RF passives. This is accomplished by using a highly-anisotropic and uniform copper plasma-etching process to remove the seed layer with no lateral etching of the copper patterns, unlike what is seen with traditional seed-layer removal by wet-etching. Application of this technical breakthrough for large-area panel processes allows demonstration of precision copper patterns demonstrated, for the first time, on organic laminates with no measurable lateral undercut. Two different plasma chemistries, one pure physical sputter-etching, and the other based upon chemical-physical processes with a hydrogen plasma, were investigated and compared.

Fundamental Limits of Organic Packages and Boards and the Need for Novel Ceramic Boards for Next Generation Electronic Packaging

Abstract: The system-on-a-package (SOP) paradigm proposes a package level integration of digital, RF/analog and opto-electronic functions to address future convergent microsystems. Two major components of SOP fabrication are sequential build-up of multiple layers (4–8) of conducting copper patterns with interlayer dielectrics on a board and multiple ICs flip-chip bonded on the top layer. A wide range of passives, wave-guides and other RF and opto-electronic components buried within the dielectric layers provide the multiple functions on a single microminiaturized platform. The routing of future nanoscale ICs with 10,000+ I/Os require multiple build-up layers of ultra fine board feature sizes of 10 μm lines/space widths and 40 μm pad diameters. Current FR4 boards cannot achieve this build-up technology because of dimensional instability during processing. These boards also undergo high warpage during the sequential build-up process which limits the fine-line lithography and also causes misalignment between the vias and their corresponding landing pads. In addition, the CTE mismatch between the silicon die and the board leads to IC-package interconnect reliability concerns, particularly in future fine-pitch assemblies where underfilling becomes complicated and expensive. This work reports experimental and analytical work comparing the performance of organic and novel ceramic boards for SOP requirements. The property requirements as deduced from these results indicate that a high stiffness and tailorable CTE from 2–4 ppm/∘C is required to enable SOP microminiaturized board fabrication and assembly without underfill. A novel ceramic board technology is proposed to address these requirements.

Highly-Effective Integrated EMI Shields with Graphene and Nanomagnetic Multilayered Composites

Abstract: Electromagnetic interference (EMI) control is one of the most significant challenges for emerging consumer, automotive, Internet of things (IoT) and wearable systems. This paper demonstrates miniaturized and integrated nanostructures for component-level EMI isolation and external EMI shielding in ultra-miniaturized electronic systems. Multi-layered nanomagnetic and copper shielding materials are designed, synthesized, and characterized for their shielding effectiveness. Graphene is explored as an alternative EMI shield material. From the modeling and experimental analysis, the advantages of nanostructures for internal and external component-level shielding in different applications is discussed.

Design and demonstration of low cost, panel-based polycrystalline silicon interposer with through-package-vias (TPVs)

Abstract: This paper for the first time proposes and demonstrates the use of panel-based polycrystalline silicon interposers for highest I/Os at lowest cost. Such an interposer is targeted at roughly a 10× lower cost compared to wafer based silicon interposers with through silicon vias (TSVs) and back end of line (BEOL) re-distribution layers (RDL). Laser via ablation was used to demonstrate through package vias (TPVs) as small as 10μm diameter in 220μm thin polycrystalline silicon panels made without any chemical-mechanical polishing (CMP). A thick polymer via liner and stress buffer layer was formed in the silicon TPVs to replace oxide liners and diffusion barriers used in TSVs. A panel silicon interposer test vehicle process demonstrator was fabricated and initial electrical measurements indicate much lower loss compared to CMOS silicon interposer with thin oxide liners. Electrical and mechanical design and modeling was also carried out to provide design guidelines for TPV formation.

Modeling, design, fabrication and characterization of first large 2.5D glass interposer as a superior alternative to silicon and organic interposers at 50 micron bump pitch

Abstract: This paper describes the first design and fabrication of a large 25D glass interposer with 50 µm pitch chip-level interconnections made of 6 layers of 3 µm re-distribution (RDL) wiring Many applications including high-performance networking and cloud computing data centers require ultra- high-bandwidth of the magnitude of 512 GB/s Silicon-based 25D interposers are the only approaches being pursued by the industry to meet this need, enabled by sub-micron BEOL wiring in the wafer fabs Such interposers, however, are too expensive for most applications Glass interposers are superior to silicon interposers due to their high dimensional stability, low loss tangent, and large panel processing ultimately leading to lower cost This paper presents the design, fabrication and electrical characterization, leading to the first fabrication of 25D glass interposers with 50 µm I/O pitch with 3 µm lines Double-sided panel processing utilizing thin, low-loss dryfilm polymer dielectrics and SAP copper plating, with differential spray etching techniques, was used to fabricate 3 m wide transmission lines on 25mm x 30mm glass interposers processed on a 300 m thick 150mm x 150mm glass panels A six-metal layer test vehicle with two daisy chain, 10mm x 10mm test chips at 100 µm spacing, was fabricated and assembled by thermo-compression bonding of Cu microbumps and SnAg solder caps Ultra-fine 3 µm escape routing was demonstrated on a two-metal layer test vehicle High frequency characterization of 3 µm lines showed low loss of 012 dB/mm at 2 GHz

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Microfibre–nanowire hybrid structure for energy scavenging

Abstract: Nanodevices don't use much energy, and if the little they do need can be scavenged from vibrations associated with foot steps, heart beats, noises and air flow, a whole range of applications in personal electronics, sensing and defence technologies opens up. Energy gathering of that type requires a technology that works at low frequency range (below 10 Hz), ideally based on soft, flexible materials. A group working at Georgia Institute of Technology has now come up with a system that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing their associated nanowires together, mechanical energy is converted into electricity via a coupled piezoelectric-semiconductor process. This work shows a potential method for creating fabrics which scavenge energy from light winds and body movement. A self-powering nanosystem that harvests its operating energy from the environment is an attractive proposition for sensing, personal electronics and defence technologies1. This is in principle feasible for nanodevices owing to their extremely low power consumption2,3,4,5. Solar, thermal and mechanical (wind, friction, body movement) energies are common and may be scavenged from the environment, but the type of energy source to be chosen has to be decided on the basis of specific applications. Military sensing/surveillance node placement, for example, may involve difficult-to-reach locations, may need to be hidden, and may be in environments that are dusty, rainy, dark and/or in deep forest. In a moving vehicle or aeroplane, harvesting energy from a rotating tyre or wind blowing on the body is a possible choice to power wireless devices implanted in the surface of the vehicle. Nanowire nanogenerators built on hard substrates were demonstrated for harvesting local mechanical energy produced by high-frequency ultrasonic waves6,7. To harvest the energy from vibration or disturbance originating from footsteps, heartbeats, ambient noise and air flow, it is important to explore innovative technologies that work at low frequencies (such as <10 Hz) and that are based on flexible soft materials. Here we present a simple, low-cost approach that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing the nanowires rooted on them with respect to each other, mechanical energy is converted into electricity owing to a coupled piezoelectric–semiconductor process8,9. This work establishes a methodology for scavenging light-wind energy and body-movement energy using fabrics.

Self-powered nanowire devices.

Abstract: The lateral and vertical integration of ZnO piezoelectric nanowires allows for voltage and power outputs sufficient to power nanowire-based sensors.