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Rao Tummala

Other affiliations: Qualcomm, IBM, AVX Corporation  ...read more
Bio: Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.


Papers
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Proceedings ArticleDOI
27 May 2014
TL;DR: In this paper, the reliability of through package copper vias (TPV) with 30 μm diameter at 120 μm pitch in ultra-thin 100 μm thick glass to achieve high-density vertical interconnections in 2.5D and 3D interposers and packages was demonstrated.
Abstract: This paper reports the first demonstration of the reliability of through package copper vias (TPV) with 30 μm diameter at 120 μm pitch in ultra-thin 100 μm thick glass to achieve high-density vertical interconnections in 2.5D and 3D interposers and packages. Bare glass with 100 μm thickness was used to demonstrate the via formation, metallization and reliability of small through-package-vias. The reliability concerns at this fine pitch were addressed through modeling and design from first principles, followed by experimental validation with test-vehicle fabrication and reliability characterization. Thermo mechanical reliability of TPV was analyzed through finite element modeling to estimate stresses inside TPV during thermal cycling and provide design guidelines. For experimental validation, test samples with daisy chains of glass TPVs were fabricated and subjected to accelerated thermal cycling tests between -55°C and 125°C to assess the thermomechanical reliability. Resistance of each daisy chain was measured periodically as a method to detect failure initiation. Majority of the TPV chains passed the reliability test without significant change in resistance. TPV daisy chains that showed changes in resistance were cross-sectioned and failure analysis indicated that the early failures of TPV in glass were related to process defects coming from via-hole formation and metallization.

19 citations

Proceedings ArticleDOI
01 Oct 2019
TL;DR: In this paper, a low-loss photo-sensitive dielectric material is proposed to enable sub-10 µm photo-patterning and low dissipation factor, known as Df. This material is designed to have a comparatively low curing temperature of 200°C, high elongation >50%, and high adhesion, and low surface roughness.
Abstract: Electrically low-loss and high-density interconnection between components in a package have been one of the most critical metrics for next-generation 5G millimeterwave packages. This paper describes an innovative low-loss photosensitive dielectric material, which enables sub- $10\ \mu \mathrm{m}$ photo-patterning and shows low dissipation factor, known as Df. Dielectric properties providing low-loss interconnects were characterized by ring-resonator method. The results showed a dielectric constant (Dk) of 2.8 and a dissipation factor (Df) of less than 0.005 up to 40 GHz. This material is also designed to have a comparatively low curing temperature of 200°C, high elongation >50%, and high adhesion, and low surface roughness. This paper also presents the demonstration of low-loss and high-density signal routings using dual damascene process with the material. The innovative photosensitive dielectric material, reported in this paper, is a promising candidate to enable high-performance, high-density fan-out and interposers for RF and 5G mm-wave applications.

19 citations

Proceedings ArticleDOI
01 Jun 2010
TL;DR: In this paper, a low-profile interconnect architecture, comprising of copper-to-copper interconnection and novel adhesive materials, was demonstrated. But scaling down the bump pitch to increase the interconnect density poses serious reliability and yield issues.
Abstract: In a continuous drive to achieve low form-factor packages, chip-to-package interconnections have evolved from the conventional solders to a more hybrid technology consisting of copper and solder. However, scaling down the bump pitch to increase the interconnect density poses serious reliability and yield issues. In the previous, a low-profile interconnect architecture, ~20µm total height, was demonstrated comprising of copper-to-copper interconnection and novel adhesive materials. This paper focuses on: (1) design and fabrication of test vehicles to assess the robustness of the interconnect architecture, (2) assembly process development for copper-to-copper interconnections, and (3) reliability and failure analysis of the interconnection. Excellent reliability results are demonstrated under thermal cycling test (TCT) using non-conductive films (NCF) as adhesive. This interconnect scheme is also shown to perform well with different die sizes, die thicknesses and with embedded dies thus offering a great potential for integration with flip chip packages as well as with chip-last embedded active chips in organic substrates. A simple and reliable low-cost and low-temperature direct Cu-Cu bonding is thus demonstrated for the first time.

19 citations

Proceedings ArticleDOI
20 Jun 2005
TL;DR: In this paper, the pros and cons of different embedded capacitance approaches through simulation are discussed and compared for a typical power/ground network with an embedded capacitor compared with that of a surface mount discrete capacitor.
Abstract: Embedded decoupling is normally considered a better solution than surface mount decoupling for suppressing the switching noise of a high speed digital board/package because of its shorter leads that result in smaller parasitic inductance. This leads to lower impedance over a higher frequency band. It is presumably better in reliability and lowers the cost as well. Designers tend to use large value capacitors for efficient decoupling. Usually, to increase capacitance of an embedded capacitor, one can use a material with higher dielectric constant, design larger electrodes, and reduce the thickness of the dielectric. However, these strategies may sometimes lead to lower performance at high frequency band. This paper will discuss the pros and cons of different embedded capacitor approaches through simulation. As an application example, a typical power/ground network with an embedded capacitor will be compared with that of surface mount discrete capacitor.

19 citations

Patent
13 Jul 2010
TL;DR: In this paper, a chip-to-substrate interconnect assembly is described, where the bump is configured to electrically interconnect at least a portion of the semiconductor with at least part of the substrate when the bump contacts with the substrate pad.
Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

18 citations


Cited by
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Journal ArticleDOI

[...]

08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

Journal ArticleDOI
TL;DR: Shape-memory polymers as discussed by the authors are an emerging class of active polymers that can change their shape in a predefined way from shape A to shape B when exposed to an appropriate stimulus.

1,575 citations

Journal ArticleDOI
14 Feb 2008-Nature
TL;DR: This work establishes a methodology for scavenging light-wind energy and body-movement energy using fabrics and presents a simple, low-cost approach that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres.
Abstract: Nanodevices don't use much energy, and if the little they do need can be scavenged from vibrations associated with foot steps, heart beats, noises and air flow, a whole range of applications in personal electronics, sensing and defence technologies opens up. Energy gathering of that type requires a technology that works at low frequency range (below 10 Hz), ideally based on soft, flexible materials. A group working at Georgia Institute of Technology has now come up with a system that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing their associated nanowires together, mechanical energy is converted into electricity via a coupled piezoelectric-semiconductor process. This work shows a potential method for creating fabrics which scavenge energy from light winds and body movement. A self-powering nanosystem that harvests its operating energy from the environment is an attractive proposition for sensing, personal electronics and defence technologies1. This is in principle feasible for nanodevices owing to their extremely low power consumption2,3,4,5. Solar, thermal and mechanical (wind, friction, body movement) energies are common and may be scavenged from the environment, but the type of energy source to be chosen has to be decided on the basis of specific applications. Military sensing/surveillance node placement, for example, may involve difficult-to-reach locations, may need to be hidden, and may be in environments that are dusty, rainy, dark and/or in deep forest. In a moving vehicle or aeroplane, harvesting energy from a rotating tyre or wind blowing on the body is a possible choice to power wireless devices implanted in the surface of the vehicle. Nanowire nanogenerators built on hard substrates were demonstrated for harvesting local mechanical energy produced by high-frequency ultrasonic waves6,7. To harvest the energy from vibration or disturbance originating from footsteps, heartbeats, ambient noise and air flow, it is important to explore innovative technologies that work at low frequencies (such as <10 Hz) and that are based on flexible soft materials. Here we present a simple, low-cost approach that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing the nanowires rooted on them with respect to each other, mechanical energy is converted into electricity owing to a coupled piezoelectric–semiconductor process8,9. This work establishes a methodology for scavenging light-wind energy and body-movement energy using fabrics.

1,473 citations

Journal ArticleDOI
TL;DR: This work demonstrates the vertical and lateral integration of ZnO nanowires into arrays that are capable of producing sufficient power to operate real devices and uses the vertically integrated nanogenerator to power a nanowire pH sensor and a Nanowire UV sensor, thus demonstrating a self-powered system composed entirely of nanowiring.
Abstract: The lateral and vertical integration of ZnO piezoelectric nanowires allows for voltage and power outputs sufficient to power nanowire-based sensors.

1,465 citations

Journal ArticleDOI
TL;DR: In this paper, the authors focus on the important role and challenges of high-k polymer-matrix composites (PMC) in new technologies and discuss potential applications of highk PMC.

1,412 citations