Rao Tummala

Bio: Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.

Accelerated SLID bonding using thin multi-layer copper-solder stack for fine-pitch interconnections

Abstract: Emerging 2.5D and 3D package-integration technologies for mobile and high-performance applications are primarily limited by advances in ultra-short and fine-pitch off-chip interconnections. A range of technologies are being pursued to advance interconnections, most notably with direct Cu-Cu interconnections or Cu pillars with solder caps. While manufacturability is still a major concern for the Cu-Cu interconnections technologies, the copper-solder approaches face limitations due to solder-bridging at fine-pitch, electromigration, and reliability issues. Thus, novel low-temperature, low-pressure, high-throughput, cost-effective and manufacturable technologies are needed to enable interconnections with pitches finer than 15 microns. This paper focuses on an innovative multi-layered copper-solder stack approach to achieve fine-pitch off-chip interconnections with no residual solders after assembly. Interconnections using this new technology enable higher current-handling because of the stable intermetallics, high-throughput assembly, and high yield even at low stand-off heights. The elimination of solder-intermetallic (IMC) interfaces is also expected to enhance the joint strength. This paper describes the design, fabrication, assembly and characterization of such stacked copper-solder interconnections. A detailed study of the effect of bonding parameters such as temperature and time on the rate of formation of stable Cu-IMC-Cu structures is presented. Test-vehicles were designed and fabricated as the first demonstration of this technology.

Low temperature sintering process for deposition of nano-structured metal for nano IC packaging

Abstract: This paper presents the study of some nano-sized metal powders, and the processes of depositing these on silicon wafers, for use in nano-structured wafer level interconnects. Nano-powders, /spl sim/50-100 nm, of copper and silver, obtained by electro-explosion of the metal wire, are used in this study. Pastes were obtained by suspension of the nano metallic powder in surfactants, organic carriers and reducing agents. The pastes were printed onto surface-treated silicon wafers and sintered at around 400/spl deg/C. Results show that there is a potential of lowering the sintering temperature to 200/spl deg/C, which would be more ideal for microelectronics applications.

Electrical Comparison between TSV in Silicon and TPV in Glass for Interposer and Package Applications

Abstract: This paper presents one of the first comprehensive studies comparing the electrical performance of through-silicon-vias (TSVs) in silicon with through-package-vias (TPVs) in glass, considering electromagnetic field distributions, 50 ohm impedance design, and the effect of via taper. First, the electric and magnetic field distributions were analyzed using a 3D EM solver (CST Microwave Studio) for the scenario of a signal via adjacent to a return via, to study the differences in the field distributions for TSVs and TPVs. Next, the design for 50 Ω impedance matching was studied with various ground-via configurations for TSVs in silicon and TPVs in glass. It was found that additional ground vias improved the impedance matching to 50 Ω in the high frequency above 40 GHz. Finally, the effect of the via taper on the impedance and insertion loss of TSVs and TPVs was studied, concluding that taper has a positive impact in the case of TSVs in lossy silicon at low frequencies as it reduces the parasitic capacitance while taper has a negative impact in the case of TSVs in intrinsic silicon and TPVs in glass, as it increases the parasitic inductance.

Fabrication and characterization of novel silicon-compatible high-density capacitors

Abstract: System integration and miniaturization demands are driving component technologies towards integrated thin films with higher volumetric efficiencies and component densities. Among the various system components, achieving higher densities with capacitors, integrated in thin film form has been a major challenge for the past few decades. This paper reports the first proof-of-concept demonstration of a novel silicon-compatible high-density capacitor technology. The key novelty stems from the tremendous enhancement in surface area from thin and porous copper nanoelectrodes and conformal alumina dielectric on such nanoelectrodes. Atomic Layer Deposition was chosen as the dielectric process because of its self-limiting, defect-free and conformal deposition on 3-D structures. Alumina with its moderate permittivity and superior dielectric properties over large voltage ranges was employed as the representative dielectric. Thin copper particulate electrodes with conformal counter electrodes showed 10 times higher capacitance density compared to the planar devices, with similar leakage properties. Thicker electrodes showed enormous enhancement in surface area but inferior leakage properties. Combination of compositional and morphological techniques was used to show alumina conformality on complex 3-D structures of copper particulate electrode. Capacitance–Voltage and Current–Voltage characterizations were carried out to confirm the feasibility of the novel high density 3-D capacitor structure.

JTEC panel report on electronic manufacturing and packaging in Japan

Abstract: Global competition in the electronics industry is offering unprecedented challenges to the industrial sector. Product lifecycles are shortening, development cycle times are decreasing, profit margins are declining, and new technology is readily available to anyone who aggressively pursues it. Japan has targeted electronics as an industry vital to its industrial success, and can, to a large degree, declare victory-particularly in the high-volume, low-cost electronic assembly industry. The question that the JTEC Electronic Packaging Panel was asked to answer was, why?. >

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Microfibre–nanowire hybrid structure for energy scavenging

Abstract: Nanodevices don't use much energy, and if the little they do need can be scavenged from vibrations associated with foot steps, heart beats, noises and air flow, a whole range of applications in personal electronics, sensing and defence technologies opens up. Energy gathering of that type requires a technology that works at low frequency range (below 10 Hz), ideally based on soft, flexible materials. A group working at Georgia Institute of Technology has now come up with a system that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing their associated nanowires together, mechanical energy is converted into electricity via a coupled piezoelectric-semiconductor process. This work shows a potential method for creating fabrics which scavenge energy from light winds and body movement. A self-powering nanosystem that harvests its operating energy from the environment is an attractive proposition for sensing, personal electronics and defence technologies1. This is in principle feasible for nanodevices owing to their extremely low power consumption2,3,4,5. Solar, thermal and mechanical (wind, friction, body movement) energies are common and may be scavenged from the environment, but the type of energy source to be chosen has to be decided on the basis of specific applications. Military sensing/surveillance node placement, for example, may involve difficult-to-reach locations, may need to be hidden, and may be in environments that are dusty, rainy, dark and/or in deep forest. In a moving vehicle or aeroplane, harvesting energy from a rotating tyre or wind blowing on the body is a possible choice to power wireless devices implanted in the surface of the vehicle. Nanowire nanogenerators built on hard substrates were demonstrated for harvesting local mechanical energy produced by high-frequency ultrasonic waves6,7. To harvest the energy from vibration or disturbance originating from footsteps, heartbeats, ambient noise and air flow, it is important to explore innovative technologies that work at low frequencies (such as <10 Hz) and that are based on flexible soft materials. Here we present a simple, low-cost approach that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing the nanowires rooted on them with respect to each other, mechanical energy is converted into electricity owing to a coupled piezoelectric–semiconductor process8,9. This work establishes a methodology for scavenging light-wind energy and body-movement energy using fabrics.

Self-powered nanowire devices.

Abstract: The lateral and vertical integration of ZnO piezoelectric nanowires allows for voltage and power outputs sufficient to power nanowire-based sensors.