Rao Tummala

Bio: Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.

Reliability Modeling and Assessment of Embedded Capacitors in Organic Substrates

Abstract: Understanding and quantifying the RLC characteristics of the embedded passives under thermomechanical deformation during fabrication and accelerated thermal conditions is necessary for their successful implementation. Embedded passives are composite layers with dissimilar material properties compared to the neighboring layers in the integral substrate. The ongoing project explores the fabrication, multifield physics-based reliability modeling and accelerated testing of embedded passive test vehicles. As a first step, in this paper, the effect of thermomechanical deformation on the electrical characteristics of embedded capacitors is studied at frequencies from 100 KHz to 2 GHz using two test vehicles. Test vehicles with embedded passives were fabricated and were subjected to accelerated thermal cycles between -55degC to 125degC, between -40degC to 125degC and high humidity and temperature conditions of 85degC/85% RH. Significant changes in the electrical parameters of the embedded capacitors are observed. The fabrication process mechanics with multiphysics global-local modeling methodology is demonstrated to study the effect of thermal cycling on the electrical characteristics of embedded capacitors. The results obtained from the multiphysics global-local modeling methodology are validated against the measured electrical characteristics of the fabricated functional test boards. The effect of changes in electrical parameters of embedded passives on system performance of low-pass filters is presented

Enabling Chip-to-Substrate All-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-Temperature Bonding

Abstract: This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) assembly. All-Cu interconnections are highly sought after to meet the escalating electrical, thermal, and reliability requirements of a wide range of emerging digital and analog systems. Such applications require low-cost processes with bonding temperatures and pressures ideally below 200°C and 20MPa, respectively, far from existing solutions established in wafer-level packaging. GT-PRC and its industry partners address this technology gap through innovative designs of bonding interfaces, introducing: 1) novel ultra-thin surface finish metallurgies applied on Cu bumps and pads to prevent oxidation and achieve low-temperature assembly, 2) low-cost fly-cut planarization technique to lower bonding pressures, and 3) low-modulus nanocopper foam caps to provide tolerance to non-coplanarities, and further reduce bonding temperatures and pressures.

Novel hydrothermal processing (<100/spl deg/C) of ceramic-polymer composites for integral capacitor applications

Abstract: Synthesis of high K thin films via low cost low temperature process remains a major challenge in realizing integral capacitors for SOP applications. The current study explores synthesis of Barium Titanate by Hydrothermal process. BaTiO/sub 3/ films using hydrothermal synthesis at temperatures less than 100/spl deg/C has been reported previously. However, these films are typically porous and hence give a very low dielectric constant and low yield. Precursor films are hence heat-treated and densified at temperatures higher than 300/spl deg/C to obtain a good yield and hence a high dielectric constant which makes these processes incompatible with organic based build-up processes. Hence the process was modified to infiltrate a polymer into these porous films to improve the yield, reliability and subsequent processing of these films. BaTiO/sub 3/ films were also synthesized on Titanium foils with the goal of integrating them with the standard PWB processes. Dielectric constant of 700 and specific capacitances more than 1000 nF/cm/sup 2/ have been achieved by this modified hydrothermal process. The microstructure of the film and the polymer infiltration can be optimized to synthesize reliable films with high dielectric constant and low loss tangent. Hence, the film morphology and thickness are being studied to optimize the processing conditions for reliable films.

Microsystems packaging from milli to microscale to nanoscale

Abstract: So called "packaging", in the past, played two roles: (1) provide I/O connections to the semiconductor devices so the IC is tested and ready for board assembly. This is called IC packaging and (2) integrate components into systems to form end product systems such as cell phones, PDAs, Laptops. This is called systems packaging. Both the above IC and systems packaging are accomplished by interconnections or wiring at the package or board level so far. Packaging is currently at milliscale in manufacturing, microscale in development and nanoscale in research. In future, the role of packaging is more than interconnections. The IC devices themselves began to integrate more and more transistors and functions, leading to what the community have been calling SOC or system-on-chip with multiple systems functions in a single chip. This can be called horizontal or 2D integration of IC blocks toward system-level functionality. The community began to realize, however, that such an approach presents design complexity and fundamental limits for computing, and integration limits for wireless systems, over the long run. This led to 3D packaging approaches, often referred to as SIP or system-in-package. Both these are the latest and most leading-edge technologies pushing the IC integration in two and three dimensions. But they both have one major shortcoming. They depend on CMOS processing and hence are limited by what can achieved with CMOS. The SIP and SOC approaches, while providing major opportunities in both miniaturization and integration for advanced portable and desktop electronic products, are limited by CMOS processes. A new concept called SOP or system-on-package being pioneered by Georgia Tech PRC - where the package, and not the board, is the entire system. SOP addresses the shortcomings of both SOC and SIP in two ways: optimize silicon for what it is good for, and the package for what it is best at, by means of IC/package/system co-design, while doing so, SOP optimizes both for cost, performance, miniaturization and reliability. The package, in this concept, therefore overcomes both computing limitations and integration limitations of SOC and SIP. It does this by having global wiring as well as RF and optical component integration in the package level, and not in the chip. The SOP, therefore, includes embedded digital, RF and optical components and functions built into a highly miniaturized package, module or board for emerging convergent systems of tomorrow. This Moore's Law for systems integration is akin to Moore's Law for ICs pushing component density by a factor of 100 to 10,000 by means of microscale thin film component integration in the short term to nanoscale integration in the long term.

Bi2 O3 and Al2 O3 containing PbO-ZnO-B2 O3 low temperature sealing glass

Abstract: Sealing glass which may be used for sealing glass plates together at relatively low temperatures. The glass has a softening temperature of about 412°C and has a thermal coefficient of expansion (from room temperature to 300°C) of about 84 × 10-7 per °C. The glass consists substantially of the following constituents in the following proportions:

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Microfibre–nanowire hybrid structure for energy scavenging

Abstract: Nanodevices don't use much energy, and if the little they do need can be scavenged from vibrations associated with foot steps, heart beats, noises and air flow, a whole range of applications in personal electronics, sensing and defence technologies opens up. Energy gathering of that type requires a technology that works at low frequency range (below 10 Hz), ideally based on soft, flexible materials. A group working at Georgia Institute of Technology has now come up with a system that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing their associated nanowires together, mechanical energy is converted into electricity via a coupled piezoelectric-semiconductor process. This work shows a potential method for creating fabrics which scavenge energy from light winds and body movement. A self-powering nanosystem that harvests its operating energy from the environment is an attractive proposition for sensing, personal electronics and defence technologies1. This is in principle feasible for nanodevices owing to their extremely low power consumption2,3,4,5. Solar, thermal and mechanical (wind, friction, body movement) energies are common and may be scavenged from the environment, but the type of energy source to be chosen has to be decided on the basis of specific applications. Military sensing/surveillance node placement, for example, may involve difficult-to-reach locations, may need to be hidden, and may be in environments that are dusty, rainy, dark and/or in deep forest. In a moving vehicle or aeroplane, harvesting energy from a rotating tyre or wind blowing on the body is a possible choice to power wireless devices implanted in the surface of the vehicle. Nanowire nanogenerators built on hard substrates were demonstrated for harvesting local mechanical energy produced by high-frequency ultrasonic waves6,7. To harvest the energy from vibration or disturbance originating from footsteps, heartbeats, ambient noise and air flow, it is important to explore innovative technologies that work at low frequencies (such as <10 Hz) and that are based on flexible soft materials. Here we present a simple, low-cost approach that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing the nanowires rooted on them with respect to each other, mechanical energy is converted into electricity owing to a coupled piezoelectric–semiconductor process8,9. This work establishes a methodology for scavenging light-wind energy and body-movement energy using fabrics.

Self-powered nanowire devices.

Abstract: The lateral and vertical integration of ZnO piezoelectric nanowires allows for voltage and power outputs sufficient to power nanowire-based sensors.