Rao Tummala

Bio: Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.

Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias

Abstract: This paper demonstrates thin glass interposers with fine pitch through package vias (TPV) as a low cost and high I/O substrate for 3D integration. Interposers for packaging of ULK and 3D-ICs need to support large numbers of die to die interconnections with I/O pitch below 50 μm. Current organic substrates are limited by CTE mismatch, wiring density, and poor dimensional stability. Wafer based silicon interposers can achieve high I/Os at fine pitch, but are limited by high cost. Glass is an ideal interposer material due to its insulating property, large panel availability and CTE match to silicon. The main focus of this work is on a) electrical and mechanical design, b) TPV and fine line formation and c) integration process and electrical characterization of thin glass interposers. This work for the first time demonstrates high throughput formation of 30 μm pitch TPVs in ultrathin glass using a parallel laser process. An integration process was demonstrated for glass interposer with polymer build-up layers on both sides. The glass interposer had stable electrical properties up to 20GHz and low insertion loss of less than 0.15dB was measured for TPVs at 9GHz.

Multichip packaging-a tutorial

Abstract: Several aspects of the multichip module technology, including its functions, leverages, applications, and markets, are reviewed All the packaging technologies used in multichip, such as sealing and encapsulation, heat removal, chip level connections, thin film, ceramic, and printed wiring, are discussed The module corrections and electrical testing used in forming a high-performance or portable system are also discussed >

A Review of 5G Front-End Systems Package Integration

Abstract: Increasing data rates, spectrum efficiency, and energy efficiency have been driving major advances in the design and hardware integration of RF communication networks. In order to meet the data rate and efficiency metrics, fifth-generation (5G) networks have emerged as a follow-on to 4G and projected to have $100\times $ higher wireless date rates and $100\times $ lower latency than those with current 4G networks. Major challenges arise in the packaging of radio frequency front-end modules because of the stringent low signal-loss requirements in the millimeter-wave frequency bands, and precision-impedance designs with smaller footprints and thickness. Heterogeneous integration in 3-D ultrathin packages with higher component densities and performance than with the existing 2-D packages is needed to realize such 5G systems. This article reviews the key building blocks of 5G systems and the underlying advances in packaging technologies to realize them.

Packaging: past, present and future

Abstract: In the past, microsystems packaging played two roles: 1) It provided I/O connections to and from devices, referred to as IC or wafer level packaging, and 2) It interconnected both active and passive components on system level boards, referred to as systems packaging. Both were accomplished by interconnections or multilayer wiring at the package or board level. More recently, the IC devices have begun to integrate not only more and more transistors but also active and passive components on an individual chip, leading the community to believe that someday there may be a single-chip system, referred to as SOC or system-on-chip. This can be called horizontal or 2D integration of IC blocks toward systems. The community began to realize, however, that such an approach presents fundamental, engineering and investment limits and computing and integration limits for wireless and wired communication systems over the long run. This led to 3-D packaging approaches, often referred to as SIP or system-in-package. The SIP, while providing major opportunities in both miniaturization and integration for advanced and portable electronic products, is limited by the CMOS process just like the SOC. Some existing and emerging applications, however, include sensors, memory modules and embedded processors with DRAMs. More recent 3-D solutions, which incorporate stacked package approaches, offer solutions towards faster time-to-market and business impediments that have plagued MCM deployment for the past decade. There is a new concept which is called SOP or system-on-package. With SOP, Wit package, not the board, is the system. As such, SOP is beginning to address the shortcomings of both SOC and SIP, as well as traditional packaging which is bulky, costly, and lower in performance and reliability than ICs, in two ways: It uses CMOS-based Si for what it is good for, namely, for transistor integration, and the package, for what it is good for, namely, RF, optical and digital integration by means of IC-package-system co-design. The SOP package, therefore, overcomes both the computing limitations and integration limitations of SOC, SIP, MCM and traditional system packaging. It does this by having global wiring as well as RF, digital and optical component integration in the package, not in the chip. SOP, therefore, includes both active and passive components including embedded digital, RF and

Ultra-thin interposer assemblies with through vias

Abstract: A 3D interconnect structure comprising an ultra-thin interposer having a plurality of ultra-high density of through-via interconnections defined therein. The 3D interposer electrically connects first and second electronic devices in vertical dimension and has the same or similar through-via density as the first or second electronic devices it connects. The various embodiments of the interconnect structure allows 3D ICs to be stacked with or without TSVs and increases bandwidth between the two electronic devices as compared to other interconnect structures of the prior art. Further, the interconnect structure of the present invention is scalable, testable, thermal manageable, and can be manufactured at relatively low costs. Such a 3D structure can be used for a wide variety of applications that require a variety of heterogeneous ICs, such as logic, memory, graphics, power, wireless and sensors that cannot be integrated into single ICs.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Microfibre–nanowire hybrid structure for energy scavenging

Abstract: Nanodevices don't use much energy, and if the little they do need can be scavenged from vibrations associated with foot steps, heart beats, noises and air flow, a whole range of applications in personal electronics, sensing and defence technologies opens up. Energy gathering of that type requires a technology that works at low frequency range (below 10 Hz), ideally based on soft, flexible materials. A group working at Georgia Institute of Technology has now come up with a system that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing their associated nanowires together, mechanical energy is converted into electricity via a coupled piezoelectric-semiconductor process. This work shows a potential method for creating fabrics which scavenge energy from light winds and body movement. A self-powering nanosystem that harvests its operating energy from the environment is an attractive proposition for sensing, personal electronics and defence technologies1. This is in principle feasible for nanodevices owing to their extremely low power consumption2,3,4,5. Solar, thermal and mechanical (wind, friction, body movement) energies are common and may be scavenged from the environment, but the type of energy source to be chosen has to be decided on the basis of specific applications. Military sensing/surveillance node placement, for example, may involve difficult-to-reach locations, may need to be hidden, and may be in environments that are dusty, rainy, dark and/or in deep forest. In a moving vehicle or aeroplane, harvesting energy from a rotating tyre or wind blowing on the body is a possible choice to power wireless devices implanted in the surface of the vehicle. Nanowire nanogenerators built on hard substrates were demonstrated for harvesting local mechanical energy produced by high-frequency ultrasonic waves6,7. To harvest the energy from vibration or disturbance originating from footsteps, heartbeats, ambient noise and air flow, it is important to explore innovative technologies that work at low frequencies (such as <10 Hz) and that are based on flexible soft materials. Here we present a simple, low-cost approach that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing the nanowires rooted on them with respect to each other, mechanical energy is converted into electricity owing to a coupled piezoelectric–semiconductor process8,9. This work establishes a methodology for scavenging light-wind energy and body-movement energy using fabrics.

Self-powered nanowire devices.

Abstract: The lateral and vertical integration of ZnO piezoelectric nanowires allows for voltage and power outputs sufficient to power nanowire-based sensors.