Rao Tummala

TL;DR: In this article, a family of sealing glasses which may be used for sealing glass plates together at relatively low temperatures is described, and they all have softening temperatures in the range 415 DEG -428 DEG C and thermal coefficients of expansion (in the range of 80-83 x 10 7 per DEGC).

TL;DR: In this paper, the authors focus on evolving the best possible criteria for selecting high electrical performance 100 micron pitch lead free solder bumping process, which is achieved through modeling and simulating the pad, process, reliability and test strategy Coplanar waveguides (CPW) were modeled to evolve process criteria for pad design and choice of materials Polyimide was chosen as the passivation on the chip Further signal parasitics were studied for the passivies and a selection criterion was evolved for its thickness.

TL;DR: There is a need to couple ultra-high density of interconnections such as from wafer-based foundries with high-throughput panel manufacturing so as to end up with highest performance at lowest cost, even for larger ICs and packages and with very high I/O density.

TL;DR: In this article, the authors demonstrate three methods to prevent cracking induced by redistribution layer (RDL) stress and dicing defect in glass substrates for RDL build-up up to $90

TL;DR: In this paper, an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on multilayered microvia organic substrate is presented, and reliability assessments of thermal shock and temperature humidity tests based on JED EC standards are presented.