Rao Tummala

Bio: Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.

Co-W as an advanced barrier for intermetallics and electromigration in fine-pitch flipchip interconnections

Abstract: The trend towards thinner packages with embedded active components in case of RF modules, and higher I/O densities in case of multicore processors or 3D ICs, are pushing interconnection technologies to its fundamental limits. The limitations of traditional solder bump technologies in terms of its fatigue resistance, current-handling, electromigration and thermomigration resistance has shifted the interconnection focus to advanced thick copper bump UBMs with solder caps. However, even these interconnections fail to meet thermo-mechanical and electrical reliability requirements for fine-pitch flipchip interconnections at high current densities where electromigration becomes a major concern. This paper explores Co-W as an advanced barrier between copper bump and solder cap for fine-pitch flipchip technology to improve electromigration resistance. By suppressing the intermetallic growth and controlling electromigration, the novel barrier is expected to enhance the current-handling and thermomechanical reliability. In a systematic experimental study, Cu-Sn diffusion and intermetallic growth rate of this new Cu-Co-W-Sn-Ag approach are compared with that of Cu-Sn-Ag with XPS depth-profiling and cross-section analysis using SEM and EDS. Based on the analysis, the benefits of Co-W as a solder barrier for fine-pitch flipchip interconnections at high current densities is presented

High throughput and fine pitch Cu-Cu interconnection technology for multichip chip-last embedding

Abstract: Ultra-thin packages with embedded actives for high functional density have become strategically important with fast growing market for portable electronics. 3D Packaging Research Center at Georgia Tech is pioneering a chip-last approach for die embedding using adhesively bonded copper bumps to enable ultra-fine pitch chip-to-package interconnections. This paper presents three advancements over the adhesive bonding technology demonstrated previously- 1) A novel method to perform chip-last at panel-level, leading to 10–15× reduction in assembly time per die, 2) Improved 2-step assembly process to achieve simultaneous die embedding and cavity planarization, and 3) Adhesive bonding of high I/O die. To demonstrate high throughput assembly, x-ray and electrical yield results for an 8–10 dies, simultaneously bonded on a 3" × 3" panel with high accuracy have been discussed. The assembly process modification yielded planarization of the gap between the die and cavity wall to <1μm. Electrical yield of adhesively bonded large die with ∼800 I/Os has also been discussed. These technology advancements aim to address some of the key limitations of conventional adhesive based assemblies, thus making chip-last adhesive bonding with low profile copper-to-copper interconnections a robust chip embedding solution for next-generation of highly integrated heterogeneous subsystems.

Fabrication of ultra-fine line circuits on PWB substrates

Abstract: One of the greatest challenges facing the packaging industry at present is the availability of organic substrates capable of routing and interconnecting high I/O fine pitch area array flip chip. These substrates require line widths and spacing of 3.5 to 12 /spl mu/m for flip chip systems applications supporting chip I/O densities of 5 K-10 K/cm/sup 2/ and pitch of 50 to 100 /spl mu/m. The system-on-a-package (SOP) module being developed at the Packaging Research Center (PRC) at Georgia Tech is focused on providing lines and spaces in the 6 to 10 /spl mu/m range and microvias in the 10 to 15 /spl mu/m range to support these applications. The PRC has been evaluating low cost materials and processes by integrating them into the SOP substrates. These substrates demonstrate the very fine and ultra fine line widths and spaces necessary to meet next-generation interconnect density requirements. Line widths and spaces of 15 to 25 /spl mu/m and microvia diameters of 50 /spl mu/m on low-cost organic substrates has been demonstrated in the fabrication of SOP testbed prototypes. Processes for 10 /spl mu/m fine lines and spaces coupled with 25 /spl mu/m small microvia interconnect are currently being developed for inclusion in the next phase of PRC SOP prototype test beds. The PRC plans further exploration into developing low-cost processes capable of achieving line widths and spaces of 6 to 10 /spl mu/m for inclusion into future SOP test bed prototypes. A fine line and width structure made of 4 /spl mu/m copper lines on build-up laminate (FR-4) is discussed in this paper. Additionally, we present highlights of a novel stack-via technology that enables the wiring density necessary to meet future interconnect requirements as indicated in the SIA semiconductor roadmap.

High performance organic dielectrics and high density substrates for next generation System on a Package (SOP) technology

Abstract: This paper introduces a new developmental family of thin film dielectric materials that have low dielectric constant (2.5 - 3.1 ) and low loss tangent (<0.005) at 10 GHz and discusses process development and reliability testing of a 1-2-1 substrate stack-up with versions of these high-performance developmental dielectrics (RXP-4). The variant used in these experiments is called RXP-4a. Various conditions were tried to optimize processing and reliability. Fine line structures down to 14 mum have been demonstrated. These were also found to pass reliability testing. Additionally, FE modeling was performed to understand the predicted reliability of microvias in these RXP-4 materials.

Process for preparing a copper containing sealing glass

Abstract: A copper oxide containing seal glass is formed by a controlled low temperature process which reduces the formation of seeds in the glass. In one embodiment the glass is prepared in two portions with the first portion containing the high melting oxides and the second portion containing the low melting oxides. The copper oxide is added to the second portion and the two portions are combined to form the seal glass at temperatures below about 800°C which reduces the formation of Cu 2 O crystals in the glass.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Microfibre–nanowire hybrid structure for energy scavenging

Abstract: Nanodevices don't use much energy, and if the little they do need can be scavenged from vibrations associated with foot steps, heart beats, noises and air flow, a whole range of applications in personal electronics, sensing and defence technologies opens up. Energy gathering of that type requires a technology that works at low frequency range (below 10 Hz), ideally based on soft, flexible materials. A group working at Georgia Institute of Technology has now come up with a system that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing their associated nanowires together, mechanical energy is converted into electricity via a coupled piezoelectric-semiconductor process. This work shows a potential method for creating fabrics which scavenge energy from light winds and body movement. A self-powering nanosystem that harvests its operating energy from the environment is an attractive proposition for sensing, personal electronics and defence technologies1. This is in principle feasible for nanodevices owing to their extremely low power consumption2,3,4,5. Solar, thermal and mechanical (wind, friction, body movement) energies are common and may be scavenged from the environment, but the type of energy source to be chosen has to be decided on the basis of specific applications. Military sensing/surveillance node placement, for example, may involve difficult-to-reach locations, may need to be hidden, and may be in environments that are dusty, rainy, dark and/or in deep forest. In a moving vehicle or aeroplane, harvesting energy from a rotating tyre or wind blowing on the body is a possible choice to power wireless devices implanted in the surface of the vehicle. Nanowire nanogenerators built on hard substrates were demonstrated for harvesting local mechanical energy produced by high-frequency ultrasonic waves6,7. To harvest the energy from vibration or disturbance originating from footsteps, heartbeats, ambient noise and air flow, it is important to explore innovative technologies that work at low frequencies (such as <10 Hz) and that are based on flexible soft materials. Here we present a simple, low-cost approach that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing the nanowires rooted on them with respect to each other, mechanical energy is converted into electricity owing to a coupled piezoelectric–semiconductor process8,9. This work establishes a methodology for scavenging light-wind energy and body-movement energy using fabrics.

Self-powered nanowire devices.

Abstract: The lateral and vertical integration of ZnO piezoelectric nanowires allows for voltage and power outputs sufficient to power nanowire-based sensors.