Rao Tummala

Bio: Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.

Modeling and design of an ultra-miniaturized WLAN sub-system with chip-last embedded PA and digital dies

Abstract: System integration by die-embedding within electronic packages offers significant advantages in miniaturization, cost and performance for mobile devices. This paper presents the functional design and analysis of ultra-thin packages that combine embedded actives (GaAs Power Amplifier and a baseband digital IC) with embedded passives (band-pass filters), leading to an ultra-miniaturized WLAN sub-system. This chip-last design routes embedded dies in the outer build-up layer, using Embedded MEMS Actives and Passives (EMAP) technology being developed in the Georgia Tech PRC's industry consortium, as an alternative, lower cost approach over current chip-first and chip-middle methods. Electromagnetic (EM) simulations were performed in order to tune the electrical performance of interconnections based on die specifications and package configuration. The digital package was designed with multiple power-ground pair islands to enhance noise isolation, while improving overall signal and power integrity. The embedded module designs for RF transmitter and the baseband IC measure at 2.8mm × 3.2mm × 0.25mm and 10mm × 10mm × 0.25mm respectively, achieving over 4.5× volume reduction compared to existing wire-bond packages.

In-Situ Investigation of Organic Additive Interactions in Copper Electroplating Solutions with Surface Enhanced Raman Spectroscopy (SERS)

Abstract: To meet demand for increasingly higher-performance electronics in increasingly smaller form factors, achieving higher logic-memory bandwidth and higher I/O density is required. This necessitates finer copper lines, smaller copper microvias, and fine-pitch, copper-filled through-package vias (TPVs). However, low-quality copper filling in highaspect ratio TPVs can lead to void formation and mechanical failures. This poses various material and process challenges for the achievement of high-quality copper metallization. These challenges can be addressed through a better understanding of copper deposition mechanisms and investigating the fundamental aspects of copper plating chemistry. In this study, in-situ interactions between different classes of organic additives in copper plating solutions were investigated with surface-enhanced Raman spectroscopy (SERS). A novel test set up is developed which allows for the direct observation of copper plating within a via. SERS was used to observe cases of competitive adsorption between suppressor, leveler, and accelerator additives within this ’via’. These observations are used to infer the impact of different classes of additives on viafilling performance and correlate the electrochemical behavior in the plating cell. A model is proposed to explain the relative tendencies of the differing classes of additives to adsorb to the copper surface within a via.

Board-Level Reliability of 3D through Glass via Filters During Thermal Cycling

Abstract: This paper theoretically and experimentally assesses the board-level reliability of glass-based 3D Integrated Passive Device (IPD) with TGV-based inductor capacitor (LC) filters in thermal cycling test. Important failure modes such as wellknown solder joint cracking and TGV failure as well as other failure modes such as glass cratering are investigated in this work. Through finite-element modeling, initial reliability predictions are made using a Morrow-Darveaux approach for solder fatigue life. To predict glass cratering, a stress-based approach is used. In the second part of this work, reliability experiments are conducted on fabricated samples, demonstrating reliable 3D IPD glass packages. Failure analysis has found that solder joint cracking and glass cratering have occurred, but no TGV failures have occurred. The experimental results are also compared to numerical predictions. Then, for future designs, the models are used to analyze the impact of key material and design parameters on the experimentally observed failure modes. It is predicted that reducing the glass core thickness will improve solder fatigue life and help prevent glass cratering. Also, TGVs are recommended to be kept away from solder joints to prevent glass cratering. Stress buffering of the dielectric also improves the reliability, though less than glass core thickness. By developing and correlating a model specifically for these devices, this work, for the first time, enables accurate study and optimization of key design parameters for 3D glass IPD radio frequency (RF) devices to achieve high mechanically reliability, highperformance long term evolution band devices, with potentially smaller footprint and thickness compared to current LTCC counterparts.

Low-Loss Additively-Deposited Ultra-Short Copper-Paste Interconnections in 3D Antenna-Integrated Packages for 5G and IoT Applications

Abstract: High-bandwidth 5G and 6G communication systems will inevitably migrate to 3D package architectures with backside or embedded dies and antenna-integrated packages for ultra-low losses and smaller footprints. With the trend to such 3D millimeter-wave (mm-wave) packages, the losses from the assembly and through-vias tend to dominate the overall losses. Traditional wirebond and thick solder interconnections lead to large mm-wave interconnect losses that are not acceptable for emerging 5G and 6G communications. This paper focuses on the material syntheses and process development of nanocopper interconnections with ultra-low interconnect losses for chip-last or flip-chip assembly in packages. The first part of the paper introduces the material synthesis of an innovative copper paste with shorter sintering times and temperatures. Optimized conditions are obtained to attain a conductivity of 1.4x10^7 S/m. This is equivalent to 82% increase in conductivity compared to that of solder. The surface roughness is also measured through atomic-force microscopy. Results suggest that the copper paste features higher roughness than that of solders. The second part of this paper discusses the potential of novel nanocopper paste to replace solders as a package assembly material, focusing on the effect of the conductivity and surface roughness with regard to the insertion loss in interconnection bumps. Based on the improved material properties of nanocopper paste, the model shows a 53% reduction in the dB scale at 28 GHz, by employing nanocopper paste. Die shear test for copper paste is also performed to show a high potential to replace solders as a flip-chip assembly material in both printed-circuit-board and mm-wave packaging technologies.

Demonstration of Patternable All-Cu Compliant Interconnections with Enhanced Manufacturability in Chip-to-Substrate Applications

Abstract: Emerging 2.5D and 3D package architectures for next-generation high-performance computing and digital applications require high-performance off-chip interconnections at ultra-fine pitch of less than 20µm. All-Cu interconnections are highly desirable as they have excellent electrical and thermal properties. However, current Cu-Cu fine-pitch bonding technologies have limited manufacturability, require special bonding conditions and are mainly limited to wafer-level packaging. A novel approach to realize all-Cu interconnections for chip-to-substrate assembly, utilizing patternable nanoporous copper (np-Cu) foam caps on copper pillars is presented in this paper. The np-Cu foam caps have low modulus to provide tolerance to non-coplanarities, and have very high surface energy which enables assembly at low-temperatures and pressures. The patterned np-Cu films were fabricated by chemical dealloying of co-electroplated Cu-Zn films, using standard semi-additive processing techniques. The patterned foam films were bonded to bulk-Cu at bonding temperature of 250oC for 30min with an applied pressure of 9MPa. During assembly, the np-Cu foams densified and formed good metallurgical contact with the bulk-Cu to achieve a void-free interface.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Microfibre–nanowire hybrid structure for energy scavenging

Abstract: Nanodevices don't use much energy, and if the little they do need can be scavenged from vibrations associated with foot steps, heart beats, noises and air flow, a whole range of applications in personal electronics, sensing and defence technologies opens up. Energy gathering of that type requires a technology that works at low frequency range (below 10 Hz), ideally based on soft, flexible materials. A group working at Georgia Institute of Technology has now come up with a system that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing their associated nanowires together, mechanical energy is converted into electricity via a coupled piezoelectric-semiconductor process. This work shows a potential method for creating fabrics which scavenge energy from light winds and body movement. A self-powering nanosystem that harvests its operating energy from the environment is an attractive proposition for sensing, personal electronics and defence technologies1. This is in principle feasible for nanodevices owing to their extremely low power consumption2,3,4,5. Solar, thermal and mechanical (wind, friction, body movement) energies are common and may be scavenged from the environment, but the type of energy source to be chosen has to be decided on the basis of specific applications. Military sensing/surveillance node placement, for example, may involve difficult-to-reach locations, may need to be hidden, and may be in environments that are dusty, rainy, dark and/or in deep forest. In a moving vehicle or aeroplane, harvesting energy from a rotating tyre or wind blowing on the body is a possible choice to power wireless devices implanted in the surface of the vehicle. Nanowire nanogenerators built on hard substrates were demonstrated for harvesting local mechanical energy produced by high-frequency ultrasonic waves6,7. To harvest the energy from vibration or disturbance originating from footsteps, heartbeats, ambient noise and air flow, it is important to explore innovative technologies that work at low frequencies (such as <10 Hz) and that are based on flexible soft materials. Here we present a simple, low-cost approach that converts low-frequency vibration/friction energy into electricity using piezoelectric zinc oxide nanowires grown radially around textile fibres. By entangling two fibres and brushing the nanowires rooted on them with respect to each other, mechanical energy is converted into electricity owing to a coupled piezoelectric–semiconductor process8,9. This work establishes a methodology for scavenging light-wind energy and body-movement energy using fabrics.

Self-powered nanowire devices.

Abstract: The lateral and vertical integration of ZnO piezoelectric nanowires allows for voltage and power outputs sufficient to power nanowire-based sensors.