A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems. An initial version of the force-directed scheduling algorithm at the heart of this methodology was originally presented by the authors in 1987. The latest implementation of the logarithm introduced here reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include multicycle and chained operations; mutually exclusive operations; scheduling under fixed global timing constraints with minimization of functional unit costs, minimization of register costs, and minimization of global interconnect requirements; scheduling with local time constraints (on operation pairs); scheduling under fixed hardware resource constraints; functional pipelining; and structural pipeline (use of pipeline functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach. >

Force-directed scheduling for the behavioral synthesis of ASICs

Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.

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High-Level Synthesis for FPGAs: From Prototyping to Deployment

High-level synthesis systems start with an abstract behavioral specification of a digital system and find a register-transfer level structure that realizes the given behavior. The various tasks involved in developing a register-transfer level structure from an algorithmic level specification are described. In particular, it is shown how the high-level synthesis task can be decomposed into a number of distinct but not independent subtasks. The techniques that have been developed for solving those subtasks are presented. Areas related to high-level synthesis that are still open problems are examined. >

The high-level synthesis of digital systems

The basic problem of high-level synthesis is the mapping of a behavioral description of a digital system into an RTL design consisting of a data path and a control unit. The authors introduce the FSMD model, which forms the basis for synthesis. They discuss the main considerations in a high-level synthesis environment: the input description language, the internal representation, and the main synthesis tasks-allocation, scheduling, and binding. They conclude with some problems that must be solved to make high-level synthesis a widely accepted methodology. >

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An Introduction to High-Level Synthesis

An integer linear programming (ILP) model for the scheduling problem in high-level synthesis is presented. In addition to time-constrained scheduling and resource-constrained scheduling, a scheduling problem called feasible scheduling, which provides a paradigm for exploring the solution space, is constructed. Extensive consideration is given to the following applications: scheduling with chaining, multicycle operations by nonpipelined function units, and multicycle operations by pipelined function units; functional pipelining; loop folding; mutually exclusive operations; scheduling under bus constraint; and minimizing lifetimes of variables. The complexity of the number of variables in the formulation is O(s*n) where s and n are the number of control steps and operations, respectively. Since the as soon as possible (ASAP), as late as possible (ALAP), and list scheduling techniques are used to reduce the solution space, the formulation becomes very efficient. A solution to a practical problem, such as the fifth-order filter, can be found optimally in a few seconds. >

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A formal approach to the scheduling problem in high level synthesis

A novel path-based scheduling algorithm is presented. It yields solutions with the minimum number of control steps, taking into account arbitrary constraints that limit the amount of operations in each control step. The result is a finite state machine that implements the control. Although the complexity of the algorithm is proportional to the number of paths in the control-flow graph, it is shown to be practical for large examples with thousands of nodes. >

Path-based scheduling for synthesis

High-level synthesis takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. In this tutorial we will examine the high-level synthesis task, showing how it can be decomposed into a number of distinct but not independent subtasks. Then we will present the techniques that have been developed for solving those subtasks. Finally, we will note those areas related to high-level synthesis that are still open problems.

Tutorial on high-level synthesis

I - Introduction to High-Level Synthesis.- to High-Level Synthesis.- II- Survey of High-Level Synthesis Systems.- AT&T's Algorithms to Silicon Project.- AT&T's Bridge System.- AT&T's CHARM System.- Carleton's Elf System.- Carleton's HAL System.- Carnegie Mellon's (First) CMU-DA System.- Carnegie Mellon's (Second) CMU-DA System.- Carnegie Mellon's System Architect's Workbench.- Carnegie Mellon's Facet/Emerald System.- Case Western's ADPS System.- Eindhoven Univ. of Technology's System.- GE's FACE/PISYN System.- Honeywell's V-Synth System.- IBM's ALERT System.- IBM's HIS System.- IBM's V Compiler.- IBM's Yorktown Silicon Compiler.- IIT Delhi's Synthesis System.- IMEC's CATHEDRAL-II System.- IMEC's CATHEDRAL-2nd System.- IMEC's CATHEDRAL-III System.- Linkoping University's CAMAD System.- NTT's HARP System.- Philips' PIRAMID System.- Siemens' Synthesis System.- Stanford's Flamel System.- Stanford's Olympus System.- Tsing Hua University's ALPS/LYRA/ARYL System.- Univ. of California at Berkeley's HYPER System.- Univ. of California at Berkeley's Synthesis System.- Univ. of California at Irvine's VSS.- Univ. of Illinois' Chippe/Slicer/Splicer System.- Univ. of Illinois' IBA System.- Univ. of Karlsruhe's DSL Synthesis System/CADDY System.- Univ. of Kiel's MIMOLA System.- Univ. of Paderborn's PARBUS System.- Univ. of Southern California's ADAM System.- Univ. of Texas at Austin's DAGAR System.- Univ. of Waterloo's CATREE System.- Univ. of Waterloo's VLSI CAD Tools.

A Survey of high-level synthesis systems

Path-based scheduling algorithms consider all possible sequences of operations (called paths) in a control-flow graph. Unlike most scheduling techniques used in high-level synthesis, they stress optimization across conditional branches. This paper presents several path-based algorithms. An exact algorithm finds the minimum number of control steps required for each possible path being executed. Heuristic solutions were also implemented. Extensive application of these algorithms to the benchmarks of the High-Level Synthesis Workshop showed the practical feasibility of such methods.

Raul Camposano

Papers

The high-level synthesis of digital systems

Path-based scheduling for synthesis

Tutorial on high-level synthesis

A Survey of high-level synthesis systems

Synthesis using path-based scheduling: algorithms and exercises