Ravi Pillarisetty

Bio: Ravi Pillarisetty is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 30, co-authored 252 publications receiving 4484 citations. Previous affiliations of Ravi Pillarisetty include Sony Broadcast & Professional Research Laboratories & Google.

Academic and industry research progress in germanium nanodevices

Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.

Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

Abstract: This work demonstrates the steepest subthreshold swing (SS < 60mV/decade) ever reported in a III–V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Owing to a lower source-to-channel tunnel barrier height, heterojunction III–V TFETs demonstrate steeper subthreshold swing (SS) at a given drain current (I D ) and improved drive current compared to the homojunction III–V TFETs. Electrical oxide thickness (EOT) scaling and increased source doping in tandem with tunnel barrier height reduction are shown to greatly improve the SS of the III–V TFETs and increase I D by more than 20X.

Non-planar gate all-around device and method of fabrication thereof

Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications

Abstract: This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230 cm2/V-s. The shortest 40 nm gate length (LG) transistors achieve peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V. These represent the highest Gm and fT ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.

Electronics based on two-dimensional materials

Abstract: The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Van der Waals heterostructures and devices

Abstract: Two-dimensional layered materials (2DLMs) have been a central focus of materials research since the discovery of graphene just over a decade ago. Each layer in 2DLMs consists of a covalently bonded, dangling-bond-free lattice and is weakly bound to neighbouring layers by van der Waals interactions. This makes it feasible to isolate, mix and match highly disparate atomic layers to create a wide range of van der Waals heterostructures (vdWHs) without the constraints of lattice matching and processing compatibility. Exploiting the novel properties in these vdWHs with diverse layering of metals, semiconductors or insulators, new designs of electronic devices emerge, including tunnelling transistors, barristors and flexible electronics, as well as optoelectronic devices, including photodetectors, photovoltaics and light-emitting devices with unprecedented characteristics or unique functionalities. We review the recent progress and challenges, and offer our perspective on the exploration of 2DLM-based vdWHs for future application in electronics and optoelectronics. With a dangling-bond-free surface, two dimensional layered materials (2DLMs) can enable the creation of diverse van der Waals heterostructures (vdWHs) without the conventional constraint of lattice matching or process compatibility. This Review discusses the recent advances in exploring 2DLM vdWHs for future electronics and optoelectronics.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Nanometre-scale electronics with III–V compound semiconductors

Abstract: For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Two-dimensional semiconductors for transistors

Abstract: In the quest for higher performance, the dimensions of field-effect transistors (FETs) continue to decrease. However, the reduction in size of FETs comprising 3D semiconductors is limited by the rate at which heat, generated from static power, is dissipated. The increase in static power and the leakage of current between the source and drain electrodes that causes this increase, are referred to as short-channel effects. In FETs with channels made from 2D semiconductors, leakage current is almost eliminated because all electrons are confined in atomically thin channels and, hence, are uniformly influenced by the gate voltage. In this Review, we provide a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FETs in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene. We also describe tunnelling FETs that possess extremely low-power switching behaviour and explain how they can be realized using heterostructures of 2D semiconductors. Field-effect transistors (FETs) with semiconducting channels made from 2D materials are known to have fewer problems with short-channel effects than devices comprising 3D semiconductors. In this Review, a mathematical framework to evaluate the performance of FETs is outlined with a focus on the properties of 2D materials, such as graphene, transition metal dichalcogenides, phosphorene and silicene.