R
Ray C. C. Cheung
Researcher at City University of Hong Kong
Publications - 186
Citations - 3008
Ray C. C. Cheung is an academic researcher from City University of Hong Kong. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 25, co-authored 176 publications receiving 2457 citations. Previous affiliations of Ray C. C. Cheung include Imperial College London & The Chinese University of Hong Kong.
Papers
More filters
Journal ArticleDOI
Accuracy-Guaranteed Bit-Width Optimization
TL;DR: An automated static approach for optimizing bit widths of fixed-point feedforward designs with guaranteed accuracy, called MiniBit, is presented and is demonstrated with polynomial approximation, RGB-to-YCbCr conversion, matrix multiplication, B-splines, and discrete cosine transform placed and routed on a Xilinx Virtex-4 FPGA.
Journal ArticleDOI
A Fast CU Size Decision Algorithm for the HEVC Intra Encoder
Biao Min,Ray C. C. Cheung +1 more
TL;DR: A novel fast algorithm is proposed for the CU size decision in intra coding using the global and local edge complexities in horizontal, vertical, 45° diagonal, and 135° diagonal directions to decide the partitioning of a CU.
Proceedings ArticleDOI
Reconfigurable acceleration for Monte Carlo based financial simulation
Guanglie Zhang,Philip H. W. Leong,C.H. Ho,K.H. Tsoi,C.C.C. Cheung,Dong-U Lee,Ray C. C. Cheung,Wayne Luk +7 more
TL;DR: A novel hardware accelerator for Monte Carlo (MC) simulation, based on a generic architecture, which combines speed and flexibility by integrating a pipelined MC core with an on-chip instruction processor is described.
Journal ArticleDOI
High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems
Donald Donglong Chen,Nele Mentens,Frederik Vercauteren,Sujoy Sinha Roy,Ray C. C. Cheung,Derek Pao,Ingrid Verbauwhede +6 more
TL;DR: The fast Fourier transform (FFT) with a linearithmic complexity of O(nlogn), is exploited in the design of a high-speed polynomial multiplier and a constant geometry FFT datapath is used in the computation to simplify the control of the architecture.
Journal ArticleDOI
Customizable elliptic curve cryptosystems
TL;DR: The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz.