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Author

Ren-Chieh Liu

Other affiliations: Realtek
Bio: Ren-Chieh Liu is an academic researcher from National Taiwan University. The author has contributed to research in topics: CMOS & Amplifier. The author has an hindex of 15, co-authored 20 publications receiving 976 citations. Previous affiliations of Ren-Chieh Liu include Realtek.

Papers
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Journal ArticleDOI
TL;DR: In this paper, a low insertion-loss single-pole double-throw switch in a standard 0.18/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4 and 5.8 GHz wireless local area network applications.
Abstract: A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.

212 citations

Proceedings ArticleDOI
08 Jun 2003
TL;DR: In this article, a CMOS distributed amplifier (DA) covering 0.6 to 22 GHz is presented, which achieves measured gain of 7.3 /spl plusmn/ 0.8 dB with chip area of 0.9 /spl times 1.5 mm/sup 2/ including testing pads.
Abstract: A CMOS distributed amplifier (DA) covering 0.6 to 22 GHz is presented in this paper. Cascode gain cells and m-derived matching sections are used to enhance the gain and bandwidth performance. The DA chip achieves measured gain of 7.3 /spl plusmn/ 0.8 dB with chip area of 0.9 /spl times/ 1.5 mm/sup 2/ including testing pads. The amplifier was fabricated in a standard 0.18-/spl mu/m CMOS technology and demonstrated the highest frequency and bandwidth of operation among previously reported amplifiers using regular CMOS processes to date.

157 citations

Proceedings ArticleDOI
12 Jun 2003
TL;DR: In this paper, a 0.5-14 GHz distributed amplifier using 0.18/spl +mn/0.9 dB gain with good return losses better than from 0.4 to 14 GHz was presented.
Abstract: A 0.5-14-GHz distributed amplifier (DA) using 0.18-/spl mu/m CMOS technology has been presented. It demonstrates the highest gain bandwidth product reported for a CMOS amplifier using a standard Si-based IC process. This DA chip achieves measured results of 10.6/spl plusmn/0.9 dB gain, NF between 3.4 and 5.4 dB with good return losses better than from 0.5 to 14 GHz. The measured output IP3 and P/sub ldB/ are +20 dBm and +10 dBm, respectively, from 2 to 10 GHz.

102 citations

Journal ArticleDOI
TL;DR: In this paper, a 24 GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18/spl mu/m CMOS technology, achieving a peak gain of 13.1 dB at 24 GHz and a minimum noise figure of 3.9dB at 24.3 GHz.
Abstract: A 24-GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18-/spl mu/m CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum noise figure of 3.9 dB at 24.3 GHz. The supply voltage and supply current are 1 V and 14 mA, respectively. To the author's knowledge, this LNA demonstrates the lowest noise figure among the reported LNAs in standard CMOS processes above 20 GHz.

96 citations

Journal ArticleDOI
TL;DR: This paper describes the analysis to design the cascode CMOS DA, together with the small-signal models, EM simulation of the spiral inductors on the silicon substrate, and the analysis of the cascade device.
Abstract: The designs of two fully integrated CMOS cascode distributed amplifiers (DAs) with 14-GHz and 22-GHz bandwidth are presented. Cascode gain cells and m-derived matching sections are used to enhance the gain and bandwidth performance. These amplifiers demonstrated the highest frequency and widest bandwidth of operation for amplifiers using regular CMOS processes to date. This paper also describes the analysis to design the cascode CMOS DA, together with the small-signal models, EM simulation of the spiral inductors on the silicon substrate, and the analysis of the cascode device. Good agreement between measured and simulated results was achieved for both of the DA designs.

65 citations


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Journal ArticleDOI
03 Jan 2005
TL;DR: In this paper, the effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak f/sub max/ of 135 GHz has been achieved with optimal device layout.
Abstract: This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak f/sub max/ of 135 GHz has been achieved with optimal device layout. The inductive quality factor (Q/sub L/) is proposed as a more representative metric for transmission lines, and for a standard CMOS back-end process, coplanar waveguide (CPW) lines are determined to possess a higher Q/sub L/ than microstrip lines. Techniques for accurate modeling of active and passive components at mm-wave frequencies are presented. The proposed methodology was used to design two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier achieves a peak |S/sub 21/| = 19 dB, output P/sub 1dB/ = -0.9 dBm, IIP3 = -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier achieves a peak |S/sub 21/| = 12 dB, output P/sub 1dB/ = +2.0 dBm, NF = 8.8 dB, and consumes 36 mA from a 1.5-V supply. The amplifiers were fabricated in a standard 130-nm 6-metal layer bulk-CMOS process, demonstrating that complex mm-wave circuits are possible in today's mainstream CMOS technologies.

736 citations

Journal ArticleDOI
TL;DR: An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter using a 0.18-/spl mu/m CMOS process achieves a power gain of 9.3 dB with an input match of -10 dB over the band.
Abstract: An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter is presented. Fabricated in a 0.18-/spl mu/m CMOS process, the IC prototype achieves a power gain of 9.3 dB with an input match of -10 dB over the band, a minimum noise figure of 4 dB, and an IIP3 of -6.7 dBm while consuming 9 mW.

714 citations

Journal ArticleDOI
TL;DR: In this paper, an ultra wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed.
Abstract: An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.

424 citations

Journal ArticleDOI
TL;DR: An ultra-wideband 3.1-10.6-GHz low-noise amplifier employing a broadband noise-canceling technique is presented, which achieves a power gain of 9.7 dB over a -3 dB bandwidth of 1.2-11.9-GHz and a noise figure of 4.5-5.1 dB in the entire UWB band.
Abstract: An ultra-wideband 3.1-10.6-GHz low-noise amplifier employing a broadband noise-canceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices performing noise cancellation is minimized by the systematic approach. Fabricated in a 0.18-mum CMOS process, the IC prototype achieves a power gain of 9.7 dB over a -3 dB bandwidth of 1.2-11.9-GHz and a noise figure of 4.5-5.1 dB in the entire UWB band. It consumes 20 mW from a 1.8-V supply and occupies an area of only 0.59 mm2

392 citations

Journal ArticleDOI
TL;DR: System, circuit, and device-level barriers to a low-cost 60 GHz CMOS implementation are described, potential solutions are explored, and remaining challenges are discussed.
Abstract: With the availability of 7 GHz of unlicensed spectrum around 60 GHz, there is a growing interest in using this resource for new consumer applications requiring very high-data-rate wireless transmission. Historically, the cost of the 60 GHz electronics, implemented in the compound semiconductor technology, has been prohibitively expensive. A fully integrated CMOS solution has the potential to drastically reduce costs enough to hit consumer price points. System, circuit, and device-level barriers to a low-cost 60 GHz CMOS implementation are described, potential solutions are explored, and remaining challenges are discussed.

343 citations