Renato Giacomini

Bio: Renato Giacomini is an academic researcher from Centro Universitário da FEI. The author has contributed to research in topics: Photodiode & Transistor. The author has an hindex of 6, co-authored 64 publications receiving 187 citations. Previous affiliations of Renato Giacomini include Universidade São Judas Tadeu & University of São Paulo.

Trapezoidal Cross-Sectional Influence on FinFET Threshold Voltage and Corner Effects

Abstract: Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensional structures. As a result of some fabrication-process limitations (as nonideal anisotropic overetch) some FinFETs have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections, as expected. This geometric alteration results in some device issues, like carrier profile, threshold voltage, and corner effects. This work analyzes these consequences based on three-dimensional numeric simulation of several dual-gate and triple-gate FinFETs. The simulation results show that the threshold voltage depends on the sidewall inclination angle and that this dependence varies according to the body doping level. The comer effects also depend on the inclination angle and doping level.

Modeling Silicon on Insulator MOS Transistors with Nonrectangular-Gate Layouts

Abstract: This work presents a new and simple approach for modeling silicon on insulator metal-oxide-semiconductor (MOS) dc characteristics for nonrectangular layout devices, based on decomposition of the original shape into trapezoidal parts and on an accurate but simple model of the trapezoidal layout transistor. Analytical expressions relating geometrical parameters and terminal current and voltages are presented for several shapes, such as L, U, T, and S, and other well-known devices such as the edgeless transistor and the asymmetric trapezoidal gate transistor. The proposed closed-form analytical expressions show good agreement with measured data and three-dimensional simulation results.

Illuminated to dark ratio improvement in lateral SOI PIN photodiodes at high temperatures

Abstract: This work presents a study of the illuminated to dark ratio (IDR) of lateral SOI PIN photodiodes. Measurements performed on fabricated devices show a fivefold improvement of the IDR when the devices are biased in accumulation mode and under high temperatures of operation, independently of the anode voltage. The obtained results show that the doping concentration of the intrinsic region has influence on the sensitivity of the diodes: the larger the doping concentration, the smaller the IDR. Furthermore, the photocurrent and dark current present lower values as the silicon film thickness is decreased, resulting in a further increase in the illuminated to dark ratio.

Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape

Abstract: The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (AV), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

High-order superlattices by rolling up van der Waals heterostructures.

Abstract: Two-dimensional (2D) materials1,2 and the associated van der Waals (vdW) heterostructures3-7 have provided great flexibility for integrating distinct atomic layers beyond the traditional limits of lattice-matching requirements, through layer-by-layer mechanical restacking or sequential synthesis. However, the 2D vdW heterostructures explored so far have been usually limited to relatively simple heterostructures with a small number of blocks8-18. The preparation of high-order vdW superlattices with larger number of alternating units is exponentially more difficult, owing to the limited yield and material damage associated with each sequential restacking or synthesis step8-29. Here we report a straightforward approach to realizing high-order vdW superlattices by rolling up vdW heterostructures. We show that a capillary-force-driven rolling-up process can be used to delaminate synthetic SnS2/WSe2 vdW heterostructures from the growth substrate and produce SnS2/WSe2 roll-ups with alternating monolayers of WSe2 and SnS2, thus forming high-order SnS2/WSe2 vdW superlattices. The formation of these superlattices modulates the electronic band structure and the dimensionality, resulting in a transition of the transport characteristics from semiconducting to metallic, from 2D to one-dimensional (1D), with an angle-dependent linear magnetoresistance. This strategy can be extended to create diverse 2D/2D vdW superlattices, more complex 2D/2D/2D vdW superlattices, and beyond-2D materials, including three-dimensional (3D) thin-film materials and 1D nanowires, to generate mixed-dimensional vdW superlattices, such as 3D/2D, 3D/2D/2D, 1D/2D and 1D/3D/2D vdW superlattices. This study demonstrates a general approach to producing high-order vdW superlattices with widely variable material compositions, dimensions, chirality and topology, and defines a rich material platform for both fundamental studies and technological applications.

Edge-Cloud Computing and Artificial Intelligence in Internet of Medical Things: Architecture, Technology and Application

Abstract: With the booming development of medical informatization and the ubiquitous connections in the fifth generation mobile communication technology (5G) era, the heterogeneity and explosive growth of medical data have brought huge challenges to data access, security and privacy, as well as information processing in Internet of Medical Things (IoMT). This article provides a comprehensive review of how to realize the timely processing and analysis of medical big data and the sinking of high-quality medical resources under the constraints of the existing medical environment and medical-related equipment. We mainly focus on the advantages brought by the cloud computing, edge computing and artificial intelligence technologies to the IoMT. We also explore how to rationalize the use of medical resources and the security and privacy of medical data, so that high-quality medical services can be provided to patients. Finally, we discuss the current challenges and possible future research directions in the edge-cloud computing and artificial intelligence related IoMT.

Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology

Abstract: SiGe has been widely used as stressors in source/drain (S/D) regions of Metal–Oxide-Semiconductor Field Effect Transistor (MOSFET) to enhance the channel mobility. In this study, selectively grown Si 1− x Ge x (0.33 ⩽ x ⩽ 0.35) with boron concentration of 1 × 10 20 cm −3 was used to elevate the S/D regions on bulk FinFETs in 14 nm technology node. The epitaxial quality of SiGe layers, SiGe profile and the strain amount of the SiGe layers were investigated. In order to in-situ clean the Si-fins before SiGe epitaxy, a series of prebaking experiments at temperature ranging from 740 to 825 °C were performed. The results showed that the thermal budget needs to be limited to 780–800 °C in order to avoid any damage to the shape of Si-fins but to remove the native oxide which is essential for high epitaxial quality. In this study, a kinetic gas model was also applied to predict the SiGe growth profile on Si-fins with trapezoidal shape. The input parameters for the model include growth temperature, partial pressures of reactant gases and the chip layout. By knowing the epitaxial profile, the strain to the Si-fins exerted by SiGe layers can be calculated. This is important in understanding the carrier transport in the FinFETs. The other benefit of the modeling is that it provides a cost-effective alternative for epitaxy process development as the SiGe profile can be readily predicted for any chip layout in advance.