THE DESIGN AND ANALYSIS OF EXPERIMENTS. By Oscar Kempthorne. New York, John Wiley and Sons, Inc., 1952. 631 pp. $8.50. This book by a teacher of statistics (as well as a consultant for \"experimenters\") is a comprehensive study of the philosophical background for the statistical design of experiment. It is necessary to have some facility with algebraic notation and manipulation to be able to use the volume intelligently. The problems are presented from the theoretical point of view, without such practical examples as would be helpful for those not acquainted with mathematics. The mathematical justification for the techniques is given. As a somewhat advanced treatment of the design and analysis of experiments, this volume will be interesting and helpful for many who approach statistics theoretically as well as practically. With emphasis on the \"why,\" and with description given broadly, the author relates the subject matter to the general theory of statistics and to the general problem of experimental inference. MARGARET J. ROBERTSON

The Design and Analysis of Experiments

Introduction to Electromagnetic Compatibility

Introduction to heat transfer

International Symposium on Quality Electronic Design

Here we benchmark device-to-device variation in field-effect transistors (FETs) based on monolayer MoS2 and WS2 films grown using metal-organic chemical vapor deposition process. Our study involves 230 MoS2 FETs and 160 WS2 FETs with channel lengths ranging from 5 μm down to 100 nm. We use statistical measures to evaluate key FET performance indicators for benchmarking these two-dimensional (2D) transition metal dichalcogenide (TMD) monolayers against existing literature as well as ultra-thin body Si FETs. Our results show consistent performance of 2D FETs across 1 × 1 cm2 chips owing to high quality and uniform growth of these TMDs followed by clean transfer onto device substrates. We are able to demonstrate record high carrier mobility of 33 cm2 V−1 s−1 in WS2 FETs, which is a 1.5X improvement compared to the best reported in the literature. Our experimental demonstrations confirm the technological viability of 2D FETs in future integrated circuits. Here, the authors perform a benchmark study of field-effect transistors (FETs) based on 2D transition metal dichalcogenides, i.e., 230 MoS2 and 160 WS2 FETs, and track device-to-device variations to gauge the technological viability in future integrated circuits.

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Benchmarking monolayer MoS2 and WS2 field-effect transistors.

This letter reports on the self-heating effect (SHE) characterization of high-voltage (HV) DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analyzed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 /spl mu/s and duty factor lower that 1:100. The new extraction method exploits analytical modeling and dedicated extraction plots for thermal resistance and capacitance using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are extracted in saturation region considering their dependence on SHE and external temperature. In DMOSFETs, the thermal resistance is shown to be a significant linear function of the device temperature (in our device, R/sub TH/ could increase by more than 100% over 100/spl deg/C). The thermal capacitance appears to decrease with the injected power and shows a plateau at high V/sub D/. SPICE simulations with the extracted thermal network R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method.

Self-heating characterization and extraction method for thermal resistance and capacitance in high voltage MOSFETs

This paper reports on the detailed analysis and modeling of lateral nonuniform doping present in intrinsic MOS channel of high-voltage (HV) MOSFETs, e.g., vertical (VDMOS) and lateral diffused MOS (LDMOS). It is shown that conventional long-channel MOSFET models using uniform lateral doping can never correctly model the capacitance behavior of these devices. A new analytical compact model for lateral nonuniformly doped MOSFET is reported. The intrinsic nonuniformly doped MOS model is first validated on numerical simulation and then on measured characteristics of VDMOS and LDMOS transistors including the drift region. The model shows good results in the dc and, most importantly, in the ac regime, especially in simulating the peaks on CGD, CGS, and CGG capacitances. This new model improves the accuracy of HV MOS models, especially output characteristics and during transient response (i.e., amplitude and position of peaks, as well as slope of capacitances).

Compact Modeling of Lateral Nonuniform Doping in High-Voltage MOSFETs

In this work, we present for the first time, a highly scalable general high voltage MOSFET model, which can be used for any high voltage MOSFET with extended drift region. This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, and a new general model for drift resistance. The model is validated on the measured characteristics of two widely used high voltage devices in the industry i.e. LDMOS and VDMOS devices, and implemented on commercial circuit simulators like SABER (Synopsys), ELDO (Mentor Graphics), Spectre (Cadence) and UltraSim (Cadence). The accuracy of the model is better than 10% for DC I–V and g–V characteristics and shows good behavior for all capacitances which are unique for these devices showing peaks and shift of peaks with bias variation. The model also exhibits excellent scalability with transistor width, drift length, number of fingers and temperature.

Scalable general high voltage MOSFET model including quasi-saturation and self-heating effects

This paper presents the models of the coupling between the transverse electromagnetic (TEM) field generated in the TEM cell and the arbitrarily oriented microstrip (MS) lines and coplanar waveguides (CPW). The lines are modeled in the frequency and time domain by taking into account different geometries and two types of subminiature version A connectors. The method of lines is used to calculate the capacitance matrix for the MS and CPW lines inserted in the TEM cell. The capacitance matrix is then used to calculate the inductance matrix, i.e., self- and coupling inductances. A number of simulations are performed in order to obtain the set of capacitance and inductance matrices for various line geometries. These results are fitted by using linear regression models. The closed-form equations for the coupling parameters are derived. The closed-form equations are used for the evaluation of coupling of arbitrarily oriented lines. The coupling models are compared against the measurements and found to be very accurate and can be used for efficient coupling modeling between the MS and CPW lines and TEM cell.

Characterizing the TEM Cell Electric and Magnetic Field Coupling to PCB Transmission Lines

A detailed investigation of the drift resistance evolution with the gate and drain biases in Lateral DMOS architectures is reported. The extractions are performed using the concept of intrinsic drain voltage, V/sub K/, applied to both simulated and measured data. Some new special test structures (MESDRIFT) have been designed and fabricated in order to investigate the DMOS bias-dependent drift resistance and experimentally confirm 2D numerical simulations. Some of the physical origins, associated with drift resistance dependence on gate and drain bias, are discussed. A simple yet efficient DMOS macro-modeling strategy is reported. It consists of combining a low-voltage BSIM model module with a bias-dependent series resistance described by a quasi-empirical mathematical expression. All LDMOS operation regimes (including quasi-saturation) are captured by the proposed expression and data measured on MESDRIFT is used to calibrate the BSIM and drift parameters. The methodology does not dependent on the drift architecture and can be applied to any similar asymmetric HV MOS devices.

Renaud Gillon

Papers

Self-heating characterization and extraction method for thermal resistance and capacitance in high voltage MOSFETs

Compact Modeling of Lateral Nonuniform Doping in High-Voltage MOSFETs

Scalable general high voltage MOSFET model including quasi-saturation and self-heating effects

Characterizing the TEM Cell Electric and Magnetic Field Coupling to PCB Transmission Lines

Bias-dependent drift resistance modeling for accurate DC and AC simulation of asymmetric HV-MOSFET