Renyuan Zhang

Bio: Renyuan Zhang is an academic researcher from Nara Institute of Science and Technology. The author has contributed to research in topics: Computer science & Support vector machine. The author has an hindex of 7, co-authored 40 publications receiving 188 citations. Previous affiliations of Renyuan Zhang include Japan Advanced Institute of Science and Technology & University of Tokyo.

CMOS supporting circuitries for nano-oscillator-based associative memories

Abstract: “Let physics do computing” is a promising approach to new-paradigm computing in the beyond CMOS era. Building associative memories based on the physics of nano oscillators, in particular, presents a lot of potential for intelligent information processing. In this paper, we discuss how CMOS supporting circuitries can interface the fabric of nano oscillators with digital computing world. Using CMOS ring oscillators to emulate the nano oscillator behavior, how to produce the associative memory function and to use it for image recognition is demonstrated by HSPICE simulation.

A low voltage CMOS rectifier for wirelessly powered devices

Abstract: This paper presents a low voltage CMOS full-wave rectifier for wirelessly powered devices. By using a simple comparator-controlled switch, the lowest input voltage amplitude can be reduced to 0.7V when using a standard CMOS 0.18μm process. With only one comparator, the proposed design dramatically reduces the production cost. In combination with unbalanced transistor scale, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and power efficiency near to 87%.

A low breakdown-voltage charge pump based on Cockcroft-Walton structure

Abstract: A Cockcroft-Walton type charge pump circuit is proposed in this paper. Compared with Dickson type, each transistor and capacitor in the proposed circuit just stand against the voltage less than one Vdd, so that a low break-down voltage process can be applied to this kind of charge pump to reduce the chip area cost and break-down risk. By using the proposed structure, the performances of voltage boosting efficiency and power efficiency can reach 98.9% and 87%.

Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing

Abstract: In this work, we design a programmable analog calculation unit (ACU) for approximately computing arbitrary functions with two operands. By implementing an efficient scheme of support vector regression, the target functions are retrieved by very large scale integrated circuits in one clock cycle with only 600 transistors. A set of dynamically tunable analog circuits are designed for generating various features of Gaussian kernel functions. By mixing these kernel functions, any specific complex function is computed by the regression. The ACU is designed and simulated in a standard CMOS technology for proof-of-concept. From the circuit simulation results, the proposed ACU calculates all the target functions with the average error less than 1.7%. The performances over energy, flexibility, and hardware efficiency of the proposed ACU are superior to a basic four-bit digital arithmetic logic unit and look-up table based architectures. The robustness against temperature and process variations is also presented with acceptable fluctuations on calculating results. To conveniently integrate the proposed ACUs into ordinary digital systems, we also design the compact memory circuits, which offer dual-mode (analog and binary) data storage/access.

Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism

Abstract: The feasibility of designing digitally programmable delay elements (PDEs) employing neuron-MOS mechanism is investigated in this work. By coupling the capacitors on the gate of the MOS transistor, the current flowing through the transistor can be digitally tuned without additional static power consumption. Various switching delays are generated by a clock buffer stage in this manner. Two types of neuron-MOS-based PDEs are suggested in this article. One of them is realized by directly applying capacitor-coupling technology on the transistors of an inverter as a clock buffer. The delay programmability is realized by tuning the charging/discharging current through the neuron-MOS inverter digitally. Since no additional transistor is introduced into the charging/discharging path, the performance fluctuation due to process variations on MOS transistors is reduced. The temperature effect is also partially compensated by the proposed neuron-MOS implementation. Another type of PDE circuit is proposed by employing a reliable reference-current-generator, where the neuron-MOS transistor acts as a linearly tunable resistance. A stable reference current is generated and used for charging/discharging the inverter as a clock buffer. As a result, the switching delay of the inverter is linearly programmed by digital input patterns. In general, both types of suggested PDE circuits achieve improved or fair performances over the robustness, power consumption, and linearity.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Abstract: High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Synchronized charge oscillations in correlated electron systems

Abstract: Strongly correlated phases exhibit collective carrier dynamics that if properly harnessed can enable novel functionalities and applications. In this article, we investigate the phenomenon of electrical oscillations in a prototypical MIT system, vanadium dioxide (VO2). We show that the key to such oscillatory behaviour is the ability to induce and stabilize a non-hysteretic and spontaneously reversible phase transition using a negative feedback mechanism. Further, we investigate the synchronization and coupling dynamics of such VO2 based relaxation oscillators and show, via experiment and simulation, that this coupled oscillator system exhibits rich non-linear dynamics including charge oscillations that are synchronized in both frequency and phase. Our approach of harnessing a non-hysteretic reversible phase transition region is applicable to other correlated systems exhibiting metal-insulator transitions and can be a potential candidate for oscillator based non-Boolean computing.

Clock Skew Optimization

Abstract: Conventional synchronous circuit design is predicated on the assumption that each clock signal of the same phase arrives at each memory element at exactly the same time. In a sequential VLSI circuit, due to differences in interconnect delays on the clock distribution network, this simultaneity is difficult to achieve and clock signals do not arrive at all of the registers at the same time. This is referred to as a skew in the clock. In a single-phase edge-triggered circuit, in the case where there is no clock skew, the designer must ensure that for correct operation, each input-output path of a combinational subcircuit has a delay that is less than the clock period. In the presence of skew, however, the relation grows more complex and the task of designing the combinational subcircuits becomes more involved.

Computer vision - ACCV 2007 : 8th Asian Conference on Computer Vision, Tokyo, Japan, November 18-22, 2007, proceedings

Abstract: Poster Session 4: Face/Gesture/Action Detection and Recognition.- Palmprint Recognition Under Unconstrained Scenes.- Comparative Studies on Multispectral Palm Image Fusion for Biometrics.- Learning Gabor Magnitude Features for Palmprint Recognition.- Sign Recognition Using Constrained Optimization.- Poster Session 4: Image and Video Processing.- Depth from Stationary Blur with Adaptive Filtering.- Three-Stage Motion Deblurring from a Video.- Near-Optimal Mosaic Selection for Rotating and Zooming Video Cameras.- Video Mosaicing Based on Structure from Motion for Distortion-Free Document Digitization.- Super Resolution of Images of 3D Scenecs.- Learning-Based Super-Resolution System Using Single Facial Image and Multi-resolution Wavelet Synthesis.- Poster Session 4: Segmentation and Classification.- Statistical Framework for Shot Segmentation and Classification in Sports Video.- Sports Classification Using Cross-Ratio Histograms.- A Bayesian Network for Foreground Segmentation in Region Level.- Efficient Graph Cuts for Multiclass Interactive Image Segmentation.- Feature Subset Selection for Multi-class SVM Based Image Classification.- Evaluating Multi-class Multiple-Instance Learning for Image Categorization.- Poster Session 4: Shape.- TransforMesh : A Topology-Adaptive Mesh-Based Approach to Surface Evolution.- Microscopic Surface Shape Estimation of a Transparent Plate Using a Complex Image.- Shape Recovery from Turntable Image Sequence.- Shape from Contour for the Digitization of Curved Documents.- Improved Space Carving Method for Merging and Interpolating Multiple Range Images Using Information of Light Sources of Active Stereo.- Shape Representation and Classification Using Boundary Radius Function.- A Convex Programming Approach to the Trace Quotient Problem.- Learning a Fast Emulator of a Binary Decision Process.- Multiplexed Illumination for Measuring BRDF Using an Ellipsoidal Mirror and a Projector.- Analyzing the Influences of Camera Warm-Up Effects on Image Acquisition.- Simultaneous Plane Extraction and 2D Homography Estimation Using Local Feature Transformations.- A Fast Optimal Algorithm for L 2 Triangulation.- Adaptively Determining Degrees of Implicit Polynomial Curves and Surfaces.- Determining Relative Geometry of Cameras from Normal Flows.- Poster Session 5: Geometry.- Highest Accuracy Fundamental Matrix Computation.- Sequential L ??? Norm Minimization for Triangulation.- Initial Pose Estimation for 3D Model Tracking Using Learned Objective Functions.- Multiple View Geometry for Non-rigid Motions Viewed from Translational Cameras.- Visual Odometry for Non-overlapping Views Using Second-Order Cone Programming.- Pose Estimation from Circle or Parallel Lines in a Single Image.- An Occupancy-Depth Generative Model of Multi-view Images.- Poster Session 5: Matching and Registration.- Image Correspondence from Motion Subspace Constraint and Epipolar Constraint.- Efficient Registration of Aerial Image Sequences Without Camera Priors.- Simultaneous Appearance Modeling and Segmentation for Matching People Under Occlusion.- Content-Based Matching of Videos Using Local Spatio-temporal Fingerprints.- Automatic Range Image Registration Using Mixed Integer Linear Programming.- Accelerating Pattern Matching or How Much Can You Slide?.- Poster Session 5: Recognition.- Detecting, Tracking and Recognizing License Plates.- Action Recognition for Surveillance Applications Using Optic Flow and SVM.- The Kernel Orthogonal Mutual Subspace Method and Its Application to 3D Object Recognition.- Viewpoint Insensitive Action Recognition Using Envelop Shape.- Unsupervised Identification of Multiple Objects of Interest from Multiple Images: dISCOVER.- Poster Session 5: Stereo, Range and 3D.- Fast 3-D Interpretation from Monocular Image Sequences on Large Motion Fields.- Color-Stripe Structured Light Robust to Surface Color and Discontinuity.- Stereo Vision Enabling Precise Border Localization Within a Scanline Optimization Framework.- Three Dimensional Position Measurement for Maxillofacial Surgery by Stereo X-Ray Images.- Total Absolute Gaussian Curvature for Stereo Prior.- Fast Optimal Three View Triangulation.- Stereo Matching Using Population-Based MCMC.- Dense 3D Reconstruction of Specular and Transparent Objects Using Stereo Cameras and Phase-Shift Method.- Identifying Foreground from Multiple Images.- Image and Video Matting with Membership Propagation.- Temporal Priors for Novel Video Synthesis.- Content-Based Image Retrieval by Indexing Random Subwindows with Randomized Trees.- Poster Session 6: Face/Gesture/Action Detection and Recognition.- Analyzing Facial Expression by Fusing Manifolds.- A Novel Multi-stage Classifier for Face Recognition.- Discriminant Clustering Embedding for Face Recognition with Image Sets.- Privacy Preserving: Hiding a Face in a Face.- Face Mosaicing for Pose Robust Video-Based Recognition.- Face Recognition by Using Elongated Local Binary Patterns with Average Maximum Distance Gradient Magnitude.- An Adaptive Nonparametric Discriminant Analysis Method and Its Application to Face Recognition.- Discriminating 3D Faces by Statistics of Depth Differences.- Kernel Discriminant Analysis Based on Canonical Differences for Face Recognition in Image Sets.- Person-Similarity Weighted Feature for Expression Recognition.- Converting Thermal Infrared Face Images into Normal Gray-Level Images.- Recognition of Digital Images of the Human Face at Ultra Low Resolution Via Illumination Spaces.- Poster Session 6: Math for Vision.- Crystal Vision-Applications of Point Groups in Computer Vision.- On the Critical Point of Gradient Vector Flow Snake.- A Fast and Noise-Tolerant Method for Positioning Centers of Spiraling and Circulating Vector Fields.- Interpolation Between Eigenspaces Using Rotation in Multiple Dimensions.- Conic Fitting Using the Geometric Distance.- Poster Session 6: Segmentation and Classification.- Efficiently Solving the Fractional Trust Region Problem.- Image Segmentation Using Iterated Graph Cuts Based on Multi-scale Smoothing.- Backward Segmentation and Region Fitting for Geometrical Visibility Range Estimation.- Image Segmentation Using Co-EM Strategy.- Co-segmentation of Image Pairs with Quadratic Global Constraint in MRFs.- Shape Reconstruction from Cast Shadows Using Coplanarities and Metric Constraints.- Evolving Measurement Regions for Depth from Defocus.- A New Framework for Grayscale and Colour Non-lambertian Shape-from-Shading.- A Regularized Approach to Feature Selection for Face Detection.- Iris Tracking and Regeneration for Improving Nonverbal Interface.- Face Mis-alignment Analysis by Multiple-Instance Subspace.

A Sub-500 mV Highly Efficient Active Rectifier for Energy Harvesting Applications

Abstract: This paper presents a highly efficient, ultra-low-voltage active full wave rectifier. A two-stage concept is used including a first passive stage and only one active diode as second stage. A bulk-input comparator working in the subthreshold region is used to drive the switch of the active diode. The voltage drop over the rectifier is some tens of millivolt, which results in voltage and power efficiencies of over 90%. The design was successfully implemented in an 0.35 μm CMOS technology. The measured power consumption of the comparator is 266 nW@500 mV and the minimum operating voltage is 380 mV. Input voltages with frequencies up to 10 kHz can be rectified.