An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

A detailed theoretical picture is given for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III–V channel metal-oxide-semiconductor field-effect transistors. For the technologically important in-plane biaxial and longitudinal uniaxial stress, changes in energy band splitting and warping, effective mass, and scattering are investigated by symmetry, tight-binding, and k⋅p methods. The results show both types of stress split the Si conduction band while only longitudinal uniaxial stress along ⟨110⟩ splits the Ge conduction band. The longitudinal uniaxial stress warps the conduction band in all semiconductors. The physics of the strain altered valence bands for Si, Ge, and III–V semiconductors are shown to be similar although the strain enhancement of hole mobility is largest for longitudinal uniaxial compression in ⟨110⟩ channel devices and channel materials with substantial differences between heavy and light hole masses such as Ge and GaAs. Furthermore, for all these materials,...

Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors

A film formation apparatus for a semiconductor process includes a process gas supply system configured to supply process gases. The process gas supply system includes a gas mixture tank configured to mix first and third process gases to form a mixture gas, a mixture gas supply line configured to supply the mixture gas from the gas mixture tank to a process field, a second process gas supply circuit having a second process gas supply line configured to supply a second process gas to the process field without passing through the gas mixture tank, and first and second switching valves disposed on the mixture gas supply line and the second process gas supply line, respectively. A control section controls the first and second switching valves to be opened and closed so as to alternately and pulse-wise supply the mixture gas and the second process gas to the process field.

Film formation method and apparatus for semiconductor process

A method of depositing a low dielectric constant film on a substrate and post-treating the low dielectric constant film is provided. The post-treatment includes rapidly heating the low dielectric constant film to a desired high temperature and then rapidly cooling the low dielectric constant film such that the low dielectric constant film is exposed to the desired high temperature for about five seconds or less. In one aspect, the post-treatment also includes exposing the low dielectric constant film to an electron beam treatment and/or UV radiation.

Post treatment of low k dielectric films

A dual channel gas distributor can simultaneously distribute plasma species of an first process gas and a non-plasma second process gas into a process zone of a substrate processing chamber. The gas distributor has a localized plasma box with a first inlet to receive a first process gas, and opposing top and bottom plates that are capable of being electrically biased relative to one another to define a localized plasma zone in which a plasma of the first process gas can be formed. The top plate has a plurality of spaced apart gas spreading holes to spread the first process gas across the localized plasma zone, and the bottom plate has a plurality of first outlets to distribute plasma species of the plasma of the first process gas into the process zone. A plasma isolated gas feed has a second inlet to receive the second process gas and a plurality of second outlets to pass the second process gas into the process zone. A plasma isolator is between the second inlet and second outlets to prevent formation of a plasma of the second process gas in the plasma isolated gas feed.

Mixing energized and non-energized gases for silicon nitride deposition

A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materials may be silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, or combinations thereof. The deposition is performed in a plasma enhanced chemical vapor deposition chamber and the deposition temperature is less than 450° C. The sidewall spacers so produced provide good capacity resistance, as well as excellent structural stability and hermeticity.

Method for producing gate stack sidewall spacers

A method of forming a sidewall spacer on a gate electrode of a metal oxide semiconductor device that includes striking a first plasma to form an oxide layer on a side of the gate electrode, where the first plasma is generated from a oxide gas that includes O3 and bis-(tertiarybutylamine)silane, and striking a second plasma to form a carbon-doped nitride layer on the oxide layer, where the second plasma may be generated from a nitride gas that includes NH3 and the bis-(tertiarybutylamine)silane. The first and second plasmas may be formed using plasma CVD and the bis-(tertiarybutylamine)silane flows uninterrupted between the striking of the first plasma and the striking of the second plasma.

Method for forming a low thermal budget spacer

Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately 1. The air gap may generally be formed by depositing a sacrificial material between the respective conductive elements, depositing a porous layer over the conductive elements and the sacrificial material, and then stripping the sacrificial material out of the space between the respective conductive elements through the porous layer, which leaves an air gap between the respective conductive elements. The sacrificial material may be, for example, a polymerized alpha terpinene layer, the porous layer may be, for example, a porous carbon doped oxide layer, and the stripping process may utilize a UV based curing process, for example.

Reza Arghavani

Papers

Post treatment of low k dielectric films

Mixing energized and non-energized gases for silicon nitride deposition

Method for producing gate stack sidewall spacers

Method for forming a low thermal budget spacer

Uv curing of pecvd-deposited sacrificial polymer films for air-gap ild