Reza Lotfi

Bio: Reza Lotfi is an academic researcher from Ferdowsi University of Mashhad. The author has contributed to research in topics: CMOS & Operational amplifier. The author has an hindex of 19, co-authored 106 publications receiving 1481 citations. Previous affiliations of Reza Lotfi include Yahoo! & University of Qom.

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

Abstract: The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.

Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs

Abstract: Successive-approximation analog-to-digital converters (SA-ADCs) are widely used in ultra-low-power applications. In this paper, the power consumption and the linearity of capacitive-array digital-to-analog converters (DACs) employed in SA-ADCs are analyzed. Specifically, closed-form formulas for the power consumption as well as the standard deviation of INL and DNL for three commonly-used radix-2 architectures including the effect of parasitic capacitances are presented and the structures are compared. The proposed analysis can be employed in choosing the best architecture and optimizing it in both hand calculations and computer-aided-design tools. Measurement results of previously published works as well as simulation results of a 10-bit 10 kS/s SA-ADC confirm the accuracy of the proposed equations. It will be shown that, in spite of what commonly is assumed, although the total capacitance and the power consumption of those architectures employing attenuating capacitors seem to be smaller than conventional binary-weighted structures, the linearity requirements impose much larger unit capacitance to the structure such that the entire power consumption is larger.

A Level-Crossing Based QRS-Detection Algorithm for Wearable ECG Sensors

Abstract: In this paper, an asynchronous analog-to-information conversion system is introduced for measuring the RR intervals of the electrocardiogram (ECG) signals. The system contains a modified level-crossing analog-to-digital converter and a novel algorithm for detecting the R-peaks from the level-crossing sampled data in a compressed volume of data. Simulated with MIT-BIH Arrhythmia Database, the proposed system delivers an average detection accuracy of 98.3%, a sensitivity of 98.89%, and a positive prediction of 99.4%. Synthesized in 0.13 μm CMOS technology with a 1.2 V supply voltage, the overall system consumes 622 nW with core area of 0.136 mm2 which make it suitable for wearable wireless ECG sensors in body-sensor networks.

Analysis and Design of Tunable Amplifiers for Implantable Neural Recording Applications

Abstract: In this paper, an in-depth design methodology for fully-integrated tunable low-noise amplifiers for neural recording applications is presented. In this methodology, a modified system design is proposed to optimize the area/noise/linearity performance. A novel linear pseudo-resistor with a wide range of tunability is also proposed. As a case study, a low-noise tunable and reconfigurable amplifier for neural recording applications is designed and simulated in a 0.18 $\mu{\rm m}$ complementary metal–oxide–semiconductor process in all process corners. Simulated characteristics of the amplifier include tunable gain of 54 dB, tunable high-cutoff frequency of 10 kHz, programmable low-cutoff frequency ranging from 4 to 300 Hz, and power consumption of 20.8 $\mu{\rm W}$ at 1.8 V. According to postlayout simulations, integrated input-referred noise of the amplifier is 2.6 $\mu{\rm V}_{\rm rms}$ and 2.38 $\mu{\rm V}_{\rm rms}$ over the 0.5 Hz–50 kHz frequency range for low-cutoff frequency of 4 and 300 Hz, respectively. The amplifier also provides output voltage swing of 1 ${\rm V}_{\rm P-P}$ with total harmonic distortion of -46.24 dB at 300 Hz, and -45.97 dB at 10 kHz.

A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter

Abstract: This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level. Moreover, the strength of the pull-up device is decreased when the pull-down device is pulling down the output node in order for the circuit to be functional even for the input voltage lower than the threshold voltage of a MOSFET. The operation of the proposed structure is also analytically investigated. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of 0.4 V and the high supply voltage of 1.8 V, the level shifter has a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy per transition of 327 fJ for a 1-MHz input signal.

ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars

Abstract: A number of recent efforts have attempted to design accelerators for popular machine learning algorithms, such as those involving convolutional and deep neural networks (CNNs and DNNs). These algorithms typically involve a large number of multiply-accumulate (dot-product) operations. A recent project, DaDianNao, adopts a near data processing approach, where a specialized neural functional unit performs all the digital arithmetic operations and receives input weights from adjacent eDRAM banks.This work explores an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner. While the use of crossbar memory as an analog dot-product engine is well known, no prior work has designed or characterized a full-fledged accelerator based on crossbars. In particular, our work makes the following contributions: (i) We design a pipelined architecture, with some crossbars dedicated for each neural network layer, and eDRAM buffers that aggregate data between pipeline stages. (ii) We define new data encoding techniques that are amenable to analog computations and that can reduce the high overheads of analog-to-digital conversion (ADC). (iii) We define the many supporting digital components required in an analog CNN accelerator and carry out a design space exploration to identify the best balance of memristor storage/compute, ADCs, and eDRAM storage on a chip. On a suite of CNN and DNN workloads, the proposed ISAAC architecture yields improvements of 14.8×, 5.5×, and 7.5× in throughput, energy, and computational density (respectively), relative to the state-of-the-art DaDianNao architecture.

Wearable Sensors for Human Activity Monitoring: A Review

Abstract: An increase in world population along with a significant aging portion is forcing rapid rises in healthcare costs. The healthcare system is going through a transformation in which continuous monitoring of inhabitants is possible even without hospitalization. The advancement of sensing technologies, embedded systems, wireless communication technologies, nano technologies, and miniaturization makes it possible to develop smart systems to monitor activities of human beings continuously. Wearable sensors detect abnormal and/or unforeseen situations by monitoring physiological parameters along with other symptoms. Therefore, necessary help can be provided in times of dire need. This paper reviews the latest reported systems on activity monitoring of humans based on wearable sensors and issues to be addressed to tackle the challenges.

Brief introduction to second edition of International Classification of Sleep Disorders:Diagnostic and Coding Manual

Abstract: Since the introduction of the first edition of International Classification of Sleep Disorders: Diagnostic and Coding Manual(ICSD-1)in 1990,national and international meetings were held to openly discuss the ongoing developments of sleep disorders and a new International Classification of Sleep Disorders: Diagnostic and Coding Manual(ICSD-2)was published in 2005.Compared with ICSD-1,the classification of ICSD-2 was developed in a manner compatible with new International Classification of Diseases(ICD-9 and ICD-10)and formed a coordinated system of International Classification of Diseases.The updated version was characterized by the significant improvements of its logicality and clinical practicability,and was more consistent with the International Classification of Disease.The contents of ICSD-2 were introduced in this article.

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

Abstract: The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.

A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- $\mu$ m CMOS for Medical Implant Devices

Abstract: This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-μm CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.