Circuit simulation is an indispensable part of modern IC design. The significant cost of fabrication has driven researchers to verify the chip functionality through simulation before submitting the design for final fabrication. With the impending end of Moore’s Law, researchers all over the world are looking for new devices with enhanced functionality. A plethora of promising emerging devices has been proposed in recent years. In order to leverage the full potential of such devices, circuit designers need fast, reliable models for SPICE simulation to explore different applications. Most of these new devices have complex underlying physical mechanism rendering the model development an extremely challenging task. For the models to be of practical use, they have to enable fast and accurate simulation that rules out the possibility of numerically solving a system of partial differential equations to arrive at a solution. In this chapter, we show how different modeling approaches can be used to simulate three emerging semiconductor devices namely, silicononinsulator four gate transistor(GFET), perimeter gated single photon avalanche diode (PG-SPAD) and insulator-metal transistor (IMT) device with volatile memristance. All the models have been verified against experimental /TCAD data and implemented in commercial circuit simulator.

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Modeling Emerging Semiconductor Devices for Circuit Simulation

In this paper, the effect of gate bias using potential distribution for Graphene channel Four Gate Transistor (G4-FET) and Gate-All-Around (GAA) MOSFET have been shown. Potential distribution is obtained by solving 2-D Poisson equation using COMSOL with MATLAB. The potential profile for G4-FET and GAA MOSFET have also been compared.

Effect of Gate Bias on Graphene Channel of G 4 -FET and Gate-All-Around MOSFET

The structure of silicon-on-insulator (SOI) four-gate transistor (G4-FET) and its different parameters for different biasing conditions are studied. A G4-FET simulation model was developed by Silvaco/Atlas 3-D simulator which incorporates non-ideal effects like concentration dependent mobility, Shockley-Read-Hall recombination, Auger recombination, bandgap narrowing effect. This model can be useful in measuring parameters dependency of a SOI four gate transistor.

Simulation study of SOI four gate transistor

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Modeling of drain current for graphene channel G4FET and gate-all-around MOSFET

A comparative study of two different analytical models of accumulation-mode SOI p-channel G4-FET has been reported and accuracy of the models has been observed under different parametric variation and biasing conditions A numerical model is developed by Silvaco/ATLAS 3-D simulator which incorporates various non ideal effects like concentration dependant mobility, Shockley-Read-Hall recombination, Auger recombination and bandgap narrowing effect The accuracy of the analytical models are tested by the numerical model The performance of varying different parameters like length, width, silicon thickness and gate biasing is also observed between lateral junction gates and between top and bottom gates

A comparative study of potential distribution of a thin film SOI p-channel four gate transistor

A mathematical model is developed to determine the 3-D potential distribution of a fully-depleted silicon-on-insulator (SOI) four-gate transistor (G4-FET). The potential distributions along the channel and between the junction-gates are assumed to be parabolic due to short channel effect. Using these two assumptions, the 3-D potential distribution model is developed. From the 3-D model, expression for threshold voltage is derived considering all possible charge conditions at the back surface. The proposed models successfully correlate the effect of all four gates and consider the impact of channel length, drain voltage and other device dimensions.

Three dimensional modeling of SOI four gate transistors

An analytical model is developed to determine the 3-D potential distribution of a fully-depleted silicon-on-insulator (SOI) four-gate transistor (G4-FET) The potential variations along the channel and between the junction-gates are assumed to be parabolic due to short channel effect and presence of MOS gates Using these assumptions and with necessary boundary conditions, the 3-D Poisson's equation is solved to formulate the overall expression The proposed model successfully correlates the four gates of the device and shows excellent agreement with the charge variation along the channel Slight modification also agrees with the surface potential of a DGFET

Rezwanul Huq

Papers

Three dimensional modeling of SOI four gate transistors

Analytical expression of the three-dimensional potential distribution of a SOI four-gate transistor