Rinus T. P. Lee

Bio: Rinus T. P. Lee is an academic researcher from GlobalFoundries. The author has contributed to research in topics: Schottky barrier & Contact resistance. The author has an hindex of 19, co-authored 96 publications receiving 1240 citations. Previous affiliations of Rinus T. P. Lee include SEMATECH & Georgia Tech Research Institute.

Sulfur-Induced PtSi:C/Si:C Schottky Barrier Height Lowering for Realizing N-Channel FinFETs With Reduced External Resistance

Abstract: In this letter, sulfur (S) segregation was exploited to attain a record-low electron barrier height (PhiB N) of 110 meV for platinum-based silicide contacts. Sulfur-incorporated PtSi:C/Si:C contacts were also demonstrated in strained FinFETs with Si:C source/drain stressors. Incorporation of sulfur at the PtSi:C/Si:C interface in the source/drain regions of FinFETs provides a 51% improvement in external resistances and a 45% enhancement in drive current as compared to devices without S segregation. The remarkable reduction in PhiB N is explained using charge transfer and dipole formation at the silicide/semiconductor interface with S segregation.

Scaling Challenges for Advanced CMOS Devices

Abstract: The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement

Abstract: We report the demonstration of 25 nm gate length LG tri-gate FinFETs with Si0.99C0.01 source and drain (S/D) regions. The strain-induced mobility enhancement due to the Si0.99C0.01 S/D leads to a drive current IDsat improvement of 20% at a fixed off-state current Ioff of 1times10-7 A/mum. With additional channel strain engineering, FinFETs incorporating Si0.99C0.01 S/D and a tensile-stress silicon nitride (SiN) capping etch-stop layer (ESL) achieve an IDsat enhancement of 56%

Novel Epitaxial Nickel Aluminide-Silicide with Low Schottky-Barrier and Series Resistance for Enhanced Performance of Dopant-Segregated Source/Drain N-channel MuGFETs

Abstract: We have developed a novel epitaxial nickel-aluminide silicide (NiSi2-xAlx) to reduce the Schottky-barrier height (SBH) and series resistance in n-channel MuGFETs with dopant-segregated Schottky-Barrier source/drain (DSS). 10% substitutional incorporation of Al in the Si matrix at the silicide-Si interface leads to a 37% reduction in the intrinsic SBH of nickel silicide. A further 42% effective reduction in the DSS SBH was attained with the combination of NiSi2-xAlx and DSS technology. Saturation drive current enhancement of 94% for NiSi2-xAlx DSS MuGFETs over NiSi DSS MuGFETs was achieved, attributed to SBH lowering, series resistance reduction and possibly silicide strain effects. As a result, an excellent drive current of 882 muA/mum at VGS-VT =VDS = 1.2 V was achieved for NiSi2-xAlxDSS MuGFETs with 55 nm gate length.

Threshold Voltage Shift Due to Charge Trapping in Dielectric-Gated AlGaN/GaN High Electron Mobility Transistors Examined in Au-Free Technology

Abstract: We report on the investigation of the charge trapping characteristics of dielectric-gated AlGaN/GaN high electron mobility transistors (HEMTs) with atomic layer deposited HfO2 (Tetrakis-(ethylmethylamino)hafnium and H2O precursors). The impact of process development and tool contamination in an Au-free 200-mm silicon CMOS line is discussed. The interfacial GaOxNy layer is proposed to be the primary location of long time constant traps. We examine the impact of these trap states on threshold voltage engineering of the gate stack. Enhancement mode operation of HEMTs is demonstrated, and the stability of enhancement mode is discussed.

Oxide Semiconductor Thin‐Film Transistors: A Review of Recent Advances

Abstract: Transparent electronics is today one of the most advanced topics for a wide range of device applications. The key components are wide bandgap semiconductors, where oxides of different origins play an important role, not only as passive component but also as active component, similar to what is observed in conventional semiconductors like silicon. Transparent electronics has gained special attention during the last few years and is today established as one of the most promising technologies for leading the next generation of flat panel display due to its excellent electronic performance. In this paper the recent progress in n- and p-type oxide based thin-film transistors (TFT) is reviewed, with special emphasis on solution-processed and p-type, and the major milestones already achieved with this emerging and very promising technology are summarizeed. After a short introduction where the main advantages of these semiconductors are presented, as well as the industry expectations, the beautiful history of TFTs is revisited, including the main landmarks in the last 80 years, finishing by referring to some papers that have played an important role in shaping transparent electronics. Then, an overview is presented of state of the art n-type TFTs processed by physical vapour deposition methods, and finally one of the most exciting, promising, and low cost but powerful technologies is discussed: solution-processed oxide TFTs. Moreover, a more detailed focus analysis will be given concerning p-type oxide TFTs, mainly centred on two of the most promising semiconductor candidates: copper oxide and tin oxide. The most recent data related to the production of complementary metal oxide semiconductor (CMOS) devices based on n- and p-type oxide TFT is also be presented. The last topic of this review is devoted to some emerging applications, finalizing with the main conclusions. Related work that originated at CENIMAT|I3N during the last six years is included in more detail, which has led to the fabrication of high performance n- and p-type oxide transistors as well as the fabrication of CMOS devices with and on paper.

Contact Structure of Semiconductor Device

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

System comprising a semiconductor device and structure

Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Semiconductor device and structure

Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Method for fabrication of a semiconductor device and structure

Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.