http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

Large-scale (or massive) multiple-input multiple-out put (MIMO) is expected to be one of the key technologies in next-generation multi-user cellular systems based on the upcoming 3GPP LTE Release 12 standard, for example. In this work, we propose-to the best of our knowledge-the first VLSI design enabling high-throughput data detection in single-carrier frequency-division multiple access (SC-FDMA)-based large-scale MIMO systems. We propose a new approximate matrix inversion algorithm relying on a Neumann series expansion, which substantially reduces the complexity of linear data detection. We analyze the associated error, and we compare its performance and complexity to those of an exact linear detector. We present corresponding VLSI architectures, which perform exact and approximate soft-output detection for large-scale MIMO systems with various antenna/user configurations. Reference implementation results for a Xilinx Virtex-7 XC7VX980T FPGA show that our designs are able to achieve more than 600 Mb/s for a 128 antenna, 8 user 3GPP LTE-based large-scale MIMO system. We finally provide a performance/complexity trade-off comparison using the presented FPGA designs, which reveals that the detector circuit of choice is determined by the ratio between BS antennas and users, as well as the desired error-rate performance.

Large-Scale MIMO Detection for 3GPP LTE: Algorithms and FPGA Implementations

In this article, we introduce MATLAB-based link and system level simulation environments for UMTS Long-Term Evolution (LTE). The source codes of both simulators are available under an academic non-commercial use license, allowing researchers full access to standard-compliant simulation environments. Owing to the open source availability, the simulators enable reproducible research in wireless communications and comparison of novel algorithms. In this study, we explain how link and system level simulations are connected and show how the link level simulator serves as a reference to design the system level simulator. We compare the accuracy of the PHY modeling at system level by means of simulations performed both with bit-accurate link level simulations and PHY-model-based system level simulations. We highlight some of the currently most interesting research questions for LTE, and explain by some research examples how our simulators can be applied.

/pdf/the-vienna-lte-simulators-enabling-reproducibility-in-21i8cpcxzx.pdf

The Vienna LTE simulators - Enabling reproducibility in wireless communications research

Welcome to the second installment of IJBDCN. This issue contains three research papers and a comprehensive survey article on mobile ad hoc networks. We would like to publish a couple of survey or tutorial articles per year as we believe this to be of value to our readers. Many research papers are necessarily focused and do not allow for a " panoramic " view of a particular subject. This is the gap that well-written survey or tutorial papers can fill. We are also planning a guest-edited special issue for the last quarter of this year and welcome your suggestions for future special issues of the journal. This second issue starts with a paper entitled " An Approach to Solving the Surviv-able Capacitated Network Design Problem " where Sridhar and Park studied the problem of selecting links of a network to construct primary and secondary routes for transfer of commodity traffic between nodes of the network. Their technique allows the design of survivable and cost-effective networks. In the second paper, " Query Processing Strategies for Location-Dependent Information Services " , Jayaputera and Taniar propose a new approach to generate a query result for location-dependent information services (LDIS). They argue that choosing a square as the scope of a query and dividing it into four equal regions, where a user is a center point of the scope, results in a faster searching time to find targets queried and brings a bigger chance to get rare targets. In addition, by avoiding resubmitting the same queries when the query results missed, the approach reduced bandwidth use at both the server and client sides. The third paper, " Addressing SPAM E-Mail Using Hashcash " by Curran and Honan tackles a problem experienced by most of us. The authors present the Hashcash proof-of-work approach and investigate the feasibility of implementing a solution based on that mechanism along with what they called a " cocktail " of antispam measures designed to keep junk mail under control. Finally , in the last paper, entitled " MANET: Applications, Issues, and Challenges for the Future " , Dhar presents an informative survey of mobile ad hoc networks, describing the main characteristics of those networks and how they are being used, and discussing the most pressing issues and challenges associated with these temporary wireless networks. We hope that you enjoy this and the upcoming issues of IJBDCN. Our goal is to …

International Journal of Business Data Communications and Networking

https://www.ece.rice.edu/~ys4937/distribute/2011-Integration-Turbo.pdf

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today's consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used in different standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm2 area in 65 nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.

/pdf/memory-conflict-analysis-and-implementation-of-a-re-3qf2r3av8i.pdf

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

A very low cost re-configurable hardware interleaver for two standards, 3GPP-WCMDA and 3GPP Long Term Evolution (3GPP-LTE) is presented. The interleaver is a key component of radio communication systems. Using conventional design methods, it consumes a large part of silicon area in the design of turbo encoder and decoder. The presented hardware interleaver address generation architecture, utilizes the algorithmic level hardware simplifications to achieve very low cost solution. After doing the hardware optimizations the proposed architecture consumes only 3.1 k gates with a 256 times 8 bit memory for the fully re-configurable dual standard interleaver address generator. The interleaved address is computed every clock cycle except the case of pruning (if block size is less than the row-column matrix) in 3GPP-WCDMA. In this case one additional clock cycle is consumed for valid address generation.

/pdf/dual-standard-re-configurable-hardware-interleaver-for-turbo-2sn944iadp.pdf

Dual standard re-configurable hardware interleaver for turbo decoding

This paper presents a parameterized parallel Turbo decoder for 3GPP LTE terminals. To support the high peak data-rate defined in the forthcoming 3GPP LTE standard, Turbo decoder with a throughout beyond 150Mbit/s is needed as a key component of the radio baseband chip. By exploiting the tradeoff of precision, speed and area consumption, a Turbo decoder with eight parallel SISO units is implemented to meet the throughput requirement. The turbo decoder is synthesized, placed and routed using 65nm CMOS technology. It achieves a throughput of 152Mbit/s and occupies an area of 0.7mm2 with estimated power consumption being 650mW1.

Implementation of a high-speed parallel Turbo decoder for 3GPP LTE terminals

The direct implementation of interleaver functions in WiMAX is not hardware efficient due to presence of complex functions. Also the conventional method i.e. using memories for storing the permutat ...

2-D Realization of WiMAX Channel Interleaver for Efficient Hardware Implementation

/pdf/linkoping-university-post-print-vlsi-implementation-of-a-4ycvq2u7zh.pdf

Rizwan Asghar

Papers

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

Dual standard re-configurable hardware interleaver for turbo decoding

Implementation of a high-speed parallel Turbo decoder for 3GPP LTE terminals

2-D Realization of WiMAX Channel Interleaver for Efficient Hardware Implementation

Linköping University Post Print VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless