Robert Bogdan Staszewski

Bio: Robert Bogdan Staszewski is an academic researcher from University College Dublin. The author has contributed to research in topics: Phase-locked loop & CMOS. The author has an hindex of 57, co-authored 491 publications receiving 12517 citations. Previous affiliations of Robert Bogdan Staszewski include California Institute of Technology & Huawei.

All-digital PLL and transmitter for mobile phones

Abstract: We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

Abstract: We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

Abstract: We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.

All-digital frequency synthesizer in deep-submicron CMOS

Abstract: PREFACE. 1 INTRODUCTION. 1.1 Frequency Synthesis. 1.1.1 Noise in Oscillators. 1.1.2 Frequency Synthesis Techniques. 1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver. 1.2.1 Transmitter. 1.2.2 Receiver. 1.2.3 Toward Direct Transmitter Modulation. 1.3 Frequency Synthesizers for Mobile Communications. 1.3.1 Integer-N PLL Architecture. 1.3.2 Fractional-N PLL Architecture. 1.3.3 Toward an All-Digital PLL Approach. 1.4 Implementation of an RF Synthesizer. 1.4.1 CMOS vs. Traditional RF Process Technologies. 1.4.2 Deep-Submicron CMOS. 1.4.3 Digitally Intensive Approach. 1.4.4 System Integration. 1.4.5 System Integration Challenges for Deep-Submicron CMOS. 2 DIGITALLY CONTROLLED OSCILLATOR. 2.1 Varactor in a Deep-Submicron CMOS Process. 2.2 Fully Digital Control of Oscillating Frequency. 2.3 LC Tank. 2.4 Oscillator Core. 2.5 Open-Loop Narrowband Digital-to-Frequency Conversion. 2.6 Example Implementation. 2.7 Time-Domain Mathematical Model of a DCO. 2.8 Summary. 3 NORMALIZED DCO. 3.1 Oscillator Transfer Function and Gain. 3.2 DCO Gain Estimation. 3.3 DCO Gain Normalization. 3.4 Principle of Synchronously Optimal DCO Tuning Word Retiming. 3.5 Time Dithering of DCO Tuning Input. 3.5.1 Oscillator Tune Time Dithering Principle. 3.5.2 Direct Time Dithering of Tuning Input. 3.5.3 Update Clock Dithering Scheme. 3.6 Implementation of PVT and Acquisition DCO Bits. 3.7 Implementation of Tracking DCO Bits 3.7.1 High-Speed Dithering of Fractional Varactors. 3.7.2 Dynamic Element Matching of Varactors. 3.7.3 DCO Varactor Rearrangement. 3.8 Time-Domain Model. 3.9 Summary. 4 ALL-DIGITAL PHASE-LOCKED LOOP. 4.1 Phase-Domain Operation. 4.2 Reference Clock Retiming. 4.3 Phase Detection. 4.3.1 Difference Mode of ADPLL Operation. 4.3.2 Integer-Domain Operation. 4.4 Modulo Arithmetic of the Reference and Variable Phases. 4.4.1 Variable-Phase Accumulator (PV Block). 4.5 Time-to-Digital Converter. 4.5.1 Frequency Reference Edge Estimation. 4.6 Fractional Error Estimator. 4.6.1 Fractional-Division Ratio Compensation. 4.6.2 TDC Resolution Effect on Estimated Frequency Resolution. 4.6.3 Active Removal of Fractional Spurs Through TDC (Optional). 4.7 Frequency Reference Retiming by a DCO Clock. 4.7.1 Sense Amplifier-Based Flip-Flop. 4.7.2 General Idea of Clock Retiming. 4.7.3 Implementation. 4.7.4 Time-Deferred Calculation of the Variable Phase (Optional). 4.8 Loop Gain Factor. 4.8.1 Phase-Error Dynamic Range. 4.9 Phase-Domain ADPLL Architecture. 4.9.1 Close-in Spurs Due to Injection Pulling. 4.10 PLL Frequency Response. 4.10.1 Conversion Between the s- and z-Domains. 4.11 Noise and Error Sources. 4.11.1 TDC Resolution Effect on Phase Noise. 4.11.2 Phase Noise Due to DCO SD Dithering. 4.12 Type II ADPLL. 4.12.1 PLL Frequency Response of a Type II Loop. 4.13 Higher-Order ADPLL. 4.13.1 PLL Stability Analysis. 4.14 Nonlinear Differential Term of an ADPLL. 4.14.1 Quality Monitoring of an RF Clock. 4.15 DCO Gain Estimation Using a PLL. 4.16 Gear Shifting of PLL Gain. 4.16.1 Autonomous Gear-Shifting Mechanism. 4.16.2 Extended Gear-Shifting Scheme with Zero-Phase Restart. 4.17 Edge Skipping Dithering Scheme (Optional). 4.18 Summary. 5 APPLICATION: ADPLL-BASED TRANSMITTER. 5.1 Direct Frequency Modulation of a DCO. 5.1.1 Discrete-Time Frequency Modulation. 5.1.2 Hybrid of Predictive/Closed PLL Operation. 5.1.3 Effect of FREF/CKR Clock Misalignment. 5.2 Just-in-Time DCO Gain Calculation. 5.3 GFSK Pulse Shaping of Transmitter Data. 5.3.1 Interpolative Filter Operation. 5.4 Power Amplifier. 5.5 Digital Amplitude Modulation. 5.5.1 Discrete Pulse-Slimming Control. 5.5.2 Regulation of Transmitting Power. 5.5.3 Tuning Word Adjustment. 5.5.4 Fully Digital Amplitude Control. 5.6 Going Forward: Polar Transmitter. 5.6.1 Generic Modulator. 5.6.2 Polar TX Realization. 5.7 Summary. 6 BEHAVIORAL MODELING AND SIMULATION. 6.1 Simulation Methodology. 6.2 Digital Blocks. 6.3 Support of Digital Stream Processing. 6.4 Random Number Generator. 6.5 Time-Domain Modeling of DCO Phase Noise. 6.5.1 Modeling Oscillator Jitter. 6.5.2 Modeling Oscillator Wander. 6.5.3 Modeling Oscillator Flicker (1/f ) Noise. 6.5.4 Clock Edge Divider Effects. 6.5.5 VHDL Model Realization of a DCO. 6.5.6 Support of Physical KDCO. 6.6 Modeling Metastability in Flip-Flops. 6.7 Simulation Results. 6.7.1 Time-Domain Simulations. 6.7.2 Frequency-Deviation Simulations. 6.7.3 Phase-Domain Simulations of Transmitters. 6.7.4 Synthesizer Phase-Noise Simulations. 6.8 Summary. 7 IMPLEMENTATION AND EXPERIMENTAL RESULTS. 7.1 DSP and Its RF Interface to DRP. 7.2 Transmitter Core Implementation. 7.3 IC Chip. 7.4 Evaluation Board. 7.5 Measurement Equipment. 7.6 GFSK Transmitter Performance. 7.7 Synthesizer Performance. 7.8 Synthesizer Switching Transients. 7.9 DSP-Driven Modulation. 7.10 Performance Summary. 7.11 Summary. APPENDIX A: SPURS DUE TO DCO SWITCHING. A.1 Spurs Due to DCO Modulation. APPENDIX B: GAUSSIAN PULSE-SHAPING FILTER. APPENDIX C: VHDL SOURCE CODE. C.1 DCO Level 2. C.2 Period-Controlled Oscillator. C.3 Tactical Flip-Flop. C.4 TDC Pseudo-Thermometer Output Decoder. REFERENCES. INDEX.

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

Abstract: A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.

Design Of Analog Cmos Integrated Circuits

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Design Of Analog Cmos Integrated Circuits

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All-digital PLL and transmitter for mobile phones

Abstract: We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

Abstract: We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

Abstract: This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.