Robert C. Pack

Bio: Robert C. Pack is an academic researcher from Cadence Design Systems. The author has contributed to research in topics: Lithography & Context (language use). The author has an hindex of 8, co-authored 13 publications receiving 530 citations.

Method and system for context-specific mask inspection

Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

Method and system for context-specific mask writing

Abstract: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

Hierarchical variation analysis of integrated circuits

Abstract: Technique assesses the impact of physical circuit variations, specification parameter variation, or process variations on clock, signal, and power network performance and through a hierarchical modeling and hierarchical Monte Carlo simulation method.

Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout

Abstract: A method for determining device yield of a semiconductor device design, includes determining statistics of at least one MOSFET parameter from a gate pattern, and calculating device yield from the at least one MOSFET parameter. The method provides a direct simulation link from device layout to device performance.

Method and system for critical dimension uniformity using charged particle beam lithography

Abstract: A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

Methods and systems for utilizing design data in combination with inspection data

Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

System and method for lithography simulation

Abstract: In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Entity centric computer system

Abstract: A system ( 100 ), method and media for an entity centric computer that develops, entity knowledge before analyzing, applying, distributing, maintaining, replicating and/or synchronizing said knowledge as required and/or requested.

Method and system for context-specific mask inspection

Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

Dynamic array architecture

Abstract: A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.