R
Robert C. Wong
Researcher at IBM
Publications - 69
Citations - 1838
Robert C. Wong is an academic researcher from IBM. The author has contributed to research in topics: Static random-access memory & Memory cell. The author has an hindex of 19, co-authored 69 publications receiving 1578 citations.
Papers
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Proceedings ArticleDOI
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Nicolas Loubet,Terence B. Hook,Pietro Montanini,Chun Wing Yeung,S. Kanakasabapathy,M. Guillom,Tenko Yamashita,Jingyun Zhang,Xin Miao,Junli Wang,Albert M. Young,Robin Chao,Myounggon Kang,Zuoguang Liu,Su Chen Fan,Bassem Hamieh,Stuart A. Sieg,Yann Mignot,W. Xu,Soon-Cheon Seo,Jae-Yoon Yoo,Shogo Mochizuki,Muthumanickam Sankarapandian,Ohyun Kwon,Adra Carr,Andrew M. Greene,Young-Kwan Park,Frougier Julien,Rohit Galatage,Ruqiang Bao,Jeffrey C. Shearer,Richard A. Conti,Ho Ju Song,Deok-Hyung Lee,Dexin Kong,Y. Xu,Abraham Arceo,Zhenxing Bi,Peng Xu,Raja Muthinti,James Chingwei Li,Robert C. Wong,D. Brown,P. Oldiges,Robert R. Robison,John C. Arnold,Nelson Felix,Spyridon Skordas,John G. Gaudiello,Theodorus E. Standaert,Hemanth Jagannathan,D. Corliss,Myung-Hee Na,Andreas Knorr,T. Wu,Dinesh Gupta,S. Lian,R. Divakaruni,T. Gow,C. Labelle,Seng Luan Lee,Vamsi Paruchuri,Huiming Bu,Mukesh Khare +63 more
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Proceedings ArticleDOI
SRAM cell design for stability methodology
C. Wann,Robert C. Wong,David J. Frank,Randy W. Mann,Shang-Bin Ko,P. Croce,D. Lea,D. Hoyniak,Yoo-Mi Lee,J. Toomey,M. Weybright,J. Sudijono +11 more
TL;DR: In this paper, the SRAM access disturb margin (ADM) is defined as the ratio of the magnitude of the critical current to maintain SRAM stability (I/sub CRIT/) to the sigma of I/subCRIT/.
Patent
A novel sram cell design to improve stability
TL;DR: In this paper, a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pulldown transistors and two pass-gate transistors is presented.
Patent
Finfet structure including multiple semiconductor fin channel heights
Robert C. Wong,Haining Yang +1 more
TL;DR: In this paper, a channel stop layer at the base of one of the first semiconductor fin and the second semiconductor Fin is used to simulate the channel heights of the two different channels.
Patent
Process for making and programming a flash memory array
TL;DR: In this article, N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour, each rail of diffusion defines a corresponding bit line.