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Robert Giterman

Bio: Robert Giterman is an academic researcher from École Polytechnique Fédérale de Lausanne. The author has contributed to research in topics: Static random-access memory & eDRAM. The author has an hindex of 12, co-authored 53 publications receiving 420 citations. Previous affiliations of Robert Giterman include Ben-Gurion University of the Negev & Bar-Ilan University.

Papers published on a yearly basis

Papers
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Journal ArticleDOI
TL;DR: This paper presents for the first time a fully functional GC-eDRAM array, implemented and fabricated in a 28-nm process node, based on a novel, 2-ported, 4-transistor NMOS-only bitcell with internal feedback to provide efficient operation in the target28-nm FD-SOI technology.
Abstract: Gain-cell embedded DRAM (GC-eDRAM) is a possible alternative to traditional static random access memories (SRAM). While GC-eDRAM provides high-density, low-leakage, low-voltage, and inherent2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further aggravated at scaled technologies, where increased subthreshold leakage currents and decreased in-cell storage capacitances result in faster data integrity deterioration. Therefore, integration of GC-eDRAM within modern systems is often considered to be limited to mature process technologies, where these phenomena are less detrimental. In this paper, we present for the first time a fully functional GC-eDRAM array, implemented and fabricated in a 28-nm process node. The 8-kb array is based on a novel, 2-ported, 4-transistor NMOS-only bitcell with internal feedback to provide efficient operation in the target 28-nm FD-SOI technology. The fabricated memory macro achieves more than 1.6-ms data retention time at 27 °C, which is $30\times $ longer than conventional gain-cell topologies when applied to this technology. The described 4-transistor dual-port nMOS array utilizes over 70% of the total memory macro area, while retaining almost 30% lower cell area than a single-ported 6T SRAM in the same technology.

43 citations

Journal ArticleDOI
TL;DR: This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain, and proposes full gain-cells for each of the nodes, operated at a minimum VDD.
Abstract: Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain. Minimum VDD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 μm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum VDD. We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality under parametric variations. As opposed to sub-VT operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell’s retention time. Monte Carlo simulations show that a 600mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz.

41 citations

Journal ArticleDOI
TL;DR: This paper presents the first fabricated and fully functional GC-eDRAM in a 28-nm bulk CMOS technology, which can be used with conservative (i.e., 100% reliable) computing paradigms, but also in the context of approximate computing, featuring a small silicon footprint and random access bandwidth.
Abstract: Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional static random access memory (SRAM) due to its high-density, low-leakage, and inherent two-ported operation, yet its dynamic nature leads to limited retention time and calls for periodic, power-hungry refresh cycles. This drawback is further aggravated in scaled technologies, where increased leakage currents and decreased in-cell storage capacitances lead to accelerated data integrity deterioration. The emerging approximate computing paradigm utilizes the inherent error-resilience of different applications to tolerate some errors in the stored data. Such error tolerance can be exploited to reduce the refresh rate in GC-eDRAM to achieve a substantial decrease in power consumption at the cost of an increase in cell failure probability. In this paper, we present the first fabricated and fully functional GC-eDRAM in a 28-nm bulk CMOS technology. The array, which is based on a novel mixed- $V_{T}$ four-transistor (4T) gain cell with internal feedback (IFGC) optimized for high performance, features a small silicon footprint and supports high-performance operation. The proposed memory can be used with conservative (i.e., 100% reliable) computing paradigms, but also in the context of approximate computing, featuring a small silicon footprint and random access bandwidth. Silicon measurements demonstrate successful operation at 800 MHz under a 900-mv supply while retaining between 30% and 45% lower bitcell area than a single-ported six-transistor (6T) SRAM and a two-ported six-transistor (8T) SRAM in the same technology.

39 citations

Journal ArticleDOI
TL;DR: This paper proposes the first radiation-hardened static random access memory bitcell targeted at low-voltage functionality, while maintaining high soft-error robustness, and employs a novel dual-driven separated-feedback mechanism to tolerate upsets.
Abstract: Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Radiation hardening of embedded memory blocks is commonly achieved by implementing extremely large bitcells or redundant arrays and maintaining a relatively high operating voltage; however, in addition to the resulting area overhead, this often limits the minimum operating voltage of the entire system leading to significant power consumption. In this paper, we propose the first radiation-hardened static random access memory (SRAM) bitcell targeted at low-voltage functionality, while maintaining high soft-error robustness. The proposed 13T employs a novel dual-driven separated-feedback mechanism to tolerate upsets with charge deposits as high as 500 fC at a scaled 500-mV supply voltage. A $32\times 32$ bit memory macro was designed and fabricated in a standard 0.18- $\mu \text{m}$ CMOS process, showing full read and write functionality down to the subthreshold voltage of 300 mV. This is achieved with a cell layout that is only $2\times $ larger than a reference 6T SRAM cell drawn with standard design rules.

38 citations

Journal ArticleDOI
TL;DR: A novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures is presented.
Abstract: Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, nonratioed operation, low static leakage, and two-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this brief, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated with a 2-kb memory macro that was designed and fabricated in a mature 0.18- $\mu $ m CMOS process, targeted at low-power, energy-efficient applications. The test array is powered with a single supply of 900 mV, showing a 0.8-ms worst case retention time, a 1.3-ns write-access time, and a 2.4-pW/bit retention power. The proposed topology provides a bitcell area reduction of 43%, as compared with a redrawn 6-transistor SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.

38 citations


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Posted Content
TL;DR: In this paper, the authors show that elliptic-curve cryptography implementations on mobile devices are vulnerable to electromagnetic and power side-channel attacks using a simple magnetic probe placed in proximity to the device, or a power probe on the phone's USB cable.
Abstract: We show that elliptic-curve cryptography implementations on mobile devices are vulnerable to electromagnetic and power side-channel attacks. We demonstrate full extraction of ECDSA secret signing keys from OpenSSL and CoreBitcoin running on iOS devices, and partial key leakage from OpenSSL running on Android and from iOS's CommonCrypto. These non-intrusive attacks use a simple magnetic probe placed in proximity to the device, or a power probe on the phone's USB cable. They use a bandwidth of merely a few hundred kHz, and can be performed cheaply using an audio card and an improvised magnetic probe.

103 citations

Journal ArticleDOI
TL;DR: This work designs and integrates 32 5x210 non-refresh eDRAM arrays in a row-parallel LDPC decoder suitable for the IEEE 802.11ad standard, and takes advantage of the unique memory access characteristic to design a non- Refresh e DRAM that holds data for the necessary access window, and improves its access time by trading off the excess retention time.
Abstract: The majority of the power consumption of a high-throughput LDPC decoder is spent on memory. Unlike in a general-purpose processor, the memory access in an LDPC decoder is deterministic and the access window is short. We take advantage of the unique memory access characteristic to design a non-refresh eDRAM that holds data for the necessary access window, and further improve its access time by trading off the excess retention time. The resulting 3T eDRAM cell is designed to balance wordline coupling to reliably retain data for a fast access. We integrate 32 5x210 non-refresh eDRAM arrays in a row-parallel LDPC decoder suitable for the IEEE 802.11ad standard. Memory refresh is eliminated and random access is replaced with a simple sequential addressing. With row merging and dual-frame processing, the 1.6 mm 2 65 nm LDPC decoder chip achieves a peak throughput of 9 Gb/s at 89.5 pJ/b, of which only 21% is spent on eDRAMs. With voltage and frequency scaling, the power consumption of the LDPC decoder is reduced to 37.7 mW for a 1.5 Gb/s throughput at 35.6 pJ/b.

76 citations

Journal ArticleDOI
TL;DR: Simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both single node upsets and the increased read/write access time.
Abstract: In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commercial standard process, simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both $0~\rightarrow ~1$ and $1~\rightarrow ~0$ single node upsets, with the increased read/write access time.

62 citations

Proceedings ArticleDOI
02 Jun 2019
TL;DR: A detailed design space exploration (DSE) of technology-system co-design for systolic-array accelerators focuses on practical/mature on-chip memory technologies, including SRAM, eDRAM, MRAM, and 3D vertical RRAM (VRRAM).
Abstract: Deep neural network (DNN) inference tasks have become ubiquitous workloads on mobile SoCs and demand energy-efficient hardware accelerators. Mobile DNN accelerators are heavily area-constrained, with only minimal on-chip SRAM, which results in heavy use of inefficient off-chip DRAM. With diminishing returns from conventional silicon technology scaling, emerging memory technologies that offer better area density than SRAM can boost accelerator efficiency by minimizing costly off-chip DRAM accesses. This paper presents a detailed design space exploration (DSE) of technology-system co-design for systolic-array accelerators. We focus on practical/mature on-chip memory technologies, including SRAM, eDRAM, MRAM, and 3D vertical RRAM (VRRAM). The DSE employs state-of-the-art optimizations (e.g., model compression and optimized buffer scheduling), and evaluates results on important models including ResNet-50, MobileNet, and Faster-RCNN. Compared to an SRAM/DRAM baseline, MRAM-based accelerators show up to 4.68× energy benefits (57% area overhead), while a 3D VRRAM-based design achieves 2.22 × energy benefits (33% area reduction).

62 citations