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Robert Murphree

Bio: Robert Murphree is an academic researcher from University of Arkansas. The author has contributed to research in topics: CMOS & Voltage regulator. The author has an hindex of 6, co-authored 12 publications receiving 123 citations.

Papers
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Journal ArticleDOI
TL;DR: The first SiC integrated circuit linear voltage regulator is reported in this article, which uses a 20-V supply and generates an output of 15 V, adjustable down to 10 V. The voltage regulator demonstrated load regulations of 1.49% and 9% for a 2-A load at temperatures of 25 and 300 °C, respectively.
Abstract: The first SiC integrated circuit linear voltage regulator is reported. The voltage regulator uses a 20-V supply and generates an output of 15 V, adjustable down to 10 V. It was designed for loads of up to 2 A over a temperature range of 25-225 °C. It was, however, successfully tested up to 300 °C. The voltage regulator demonstrated load regulations of 1.49% and 9% for a 2-A load at temperatures of 25 and 300 °C, respectively. However, the load regulation is less than 2% up to 300 °C for a 1-A load. The line regulation with a 2-A load at 25 and 300 °C was 17 and 296 mV/V, respectively. The regulator was fabricated in a Cree 4H-SiC 2-μm experimental process and consists of 1000, 32/2-μm NMOS depletion MOSFETs as the pass device, an integrated error amplifier with enhancement MOSFETs, and resistor loads, and uses external feedback and compensation networks to ensure operational integrity. It was designed to be integrated with high-voltage vertical power MOSFETs on the same SiC substrate. It also serves as a guide to future attempts for voltage regulation in any type of integrated SiC circuitry.

43 citations

Journal ArticleDOI
TL;DR: In this article, a high temperature voltage comparator and an operational amplifier (op-amp) in a 1.2-μm silicon carbide (SiC) CMOS process are described.
Abstract: This paper describes a high temperature voltage comparator and an operational amplifier (op-amp) in a 1.2- $\mu \text{m}$ silicon carbide (SiC) CMOS process. These circuits are used as building blocks for designing a high-temperature SiC low-side over current protection circuit. The over current protection circuit is used in the protection circuitry of a SiC FET gate driver in power converter applications. The op-amp and the comparator have been tested at 400 °C and 550 °C temperature, respectively. The op-amp has an input common-mode range of 0–11.2 V, a dc gain of 60 dB, a unity gain bandwidth of 2.3 MHz, and a phase margin of 48° at 400 °C. The comparator has a rise time and a fall time of 38 and 24 ns, respectively, at 550 °C. The over current protection circuit, implemented with these analog building blocks, is designed to sense a voltage across a sense resistor up to 0.5 V.

40 citations

Journal ArticleDOI
23 Nov 2017
TL;DR: In this paper, the emergence of wide bandgap power semiconductor devices has opened the possibilities of improved electrical performance and power density, including advances in integrated circuit design, semiconductor device modeling, 3D electronic packaging, and computer-aided design of widebandgap based electronics.
Abstract: The emergence of wide bandgap power semiconductor devices has opened the possibilities of improved electrical performance and power density. Advanced research into wide bandgap power electronics also includes advances in integrated circuit design, semiconductor device modeling, 3D electronic packaging, and computer-aided design of wide bandgap based electronics. These emerging trends are described along with some early results indicating the additional improvements possible in power density. Operation at extreme temperatures also becomes more feasible.

22 citations

Journal ArticleDOI
TL;DR: A silicon carbide pulse width modulation (PWM) signal generator in the 1.2 μm HiTSiC CMOS process developed by Raytheon Systems Ltd. features a 6-b binary input, which allows for setting a system's duty cycle.
Abstract: This paper describes a silicon carbide pulse width modulation (PWM) signal generator in the 1.2 μm HiTSiC CMOS process developed by Raytheon Systems Ltd. The design features a 6-b binary input, which allows for setting a system's duty cycle. The results presented in this paper utilize a field programmable gate array board in the test setup to dynamically set the duty cycle by controlling each bit. A control current is also available to give the user added flexibility for tuning the duty cycle. Experimental results show the duty cycle range of the PWM generator to be between 4.7% and 95.2% at 400 °C. Sustained operation of the circuit is demonstrated over a period of 50 h at 300 °C. Finally, the PWM generator is evaluated in the operation of a boost converter.

18 citations

Proceedings ArticleDOI
01 Nov 2015
TL;DR: In this article, the first operational digital to analog converter at 400°C was presented, which was designed in the Raytheon 1.2 μm CMOS HiTSiC process.
Abstract: This paper presents the first operational digital to analog converter at 400°C. The 8 bit R-2R ladder DAC was designed in the Raytheon 1.2 μm CMOS HiTSiC process. The data converter is also the first of its kind in SiC. It has been tested with a supply voltage between 12 V and 15 V, and reference voltages of 5 V to 8 V. At 400°C, the maximum measured differential non linearity (DNL) is 2 LSB (least significant bit) and the integral non linearity is 4.4 LSB.

17 citations


Cited by
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Journal ArticleDOI
01 Aug 2021
TL;DR: In this article, the authors report the monolithic integration of enhancementmode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits.
Abstract: Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters. Through the monolithic integration of enhancement-mode n-type and p-type gallium nitride field-effect transistors, complementary integrated circuits including latch circuits and ring oscillators can be created for use in high-power and high-frequency applications.

97 citations

Journal ArticleDOI
TL;DR: In this paper, two SiC vertically oriented planar gate D-MOSFETs were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to this common source of electrical stress.
Abstract: SiC MOSFETs are a leading option for increasing the power density of power electronics; however, for these devices to supersede the Si insulated-gate bipolar transistor, their characteristics have to be further understood. Two SiC vertically oriented planar gate D-MOSFETs rated for 1200 V/150 A were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to this common source of electrical stress. This research supplements recent work that demonstrated the long term reliability of these same devices [1] . Using an RLC pulse-ring-down test bed, these devices hard-switched 600 A peak current pulses, corresponding to a current density of 1500 A/cm2. Throughout testing, static characteristics of the devices such as $B_{{\rm VDSS}}$ , $R_{{\rm DS}({\rm on})}$ , and $V_{{\rm GS}({\rm th})}$ were measured with a high power device analyzer. The experimental results indicated that a conductive path was formed through the gate oxide; TCAD simulations revealed localized heating at the SiC/SiO2 interface as a result of the extreme high current density present in the device's JFET region. However, the high peak currents and repetition rates required to produce the conductive path through the gate oxide demonstrate the robustness of SiC MOSFETs under the pulsed overcurrent conditions common in power electronic applications.

83 citations

Journal ArticleDOI
TL;DR: An overview of the high-power electrical machine families and their associated power electronic converter (PEC) interfaces that are currently competing for aircraft power conversion systems and the influence of these concerns is outlined and a view of the future technology outlook is offered.
Abstract: More electric aircraft (MEA) architectures consist of several subsystems, which must all comply with the settled safety requirements of aerospace applications. Thus, achieving reliability and fault-tolerance represents the main cornerstone when classifying different solutions. Hybrid electric aircraft (HEA) extends the MEA concept by electrifying the propulsive power as well as the auxiliary power, and thereby pushing the limits of electrification. This paper gives an overview of the high-power electrical machine families and their associated power electronic converter (PEC) interfaces that are currently competing for aircraft power conversion systems. Various functionalities and starter-generator (S/G) solutions are also covered. In order to highlight the latest advancements, the efficiency of the world’s most powerful aerospace generator (Mark 1) developed within the E-Fan X HEA project is graphically represented and assessed against other rivaling solutions. Motivated by the strict requirements on efficiency, power density, trustworthiness, as well as starting functionalities, supplementary considerations on the system-level design are paramount. In order to highlight the MEA goals and take advantage of all potential benefits, all subsystems must be treated as a whole. It is then shown that the combination of PECs, aircraft grid and electrical machines can be better adapted to benefit the overall system. This survey outlines the influence of these concerns and offers a view of the future technology outlook, as well as covering the present challenges and opportunities.

72 citations

Journal ArticleDOI
TL;DR: A prototype set of essential mixed-signal ICs on SiC capable of controlling power switches and a lateral power MESFET able to operate at high temperatures, all embedded on the same chip.
Abstract: This paper is an important step toward the development of complex integrated circuit (IC) control electronics that have to attend to high-temperature environment power applications. We present in premiere a prototype set of essential mixed-signal ICs on SiC capable of controlling power switches and a lateral power MESFET able to operate at high temperatures, all embedded on the same chip. Also, we report for the first time the functionality of standard Si-CMOS topologies on SiC for the master–slave data flip-flop (FF) and data-reset FF digital building blocks designed with MESFETs. Concretely, we present the complete development of SiC-MESFET IC circuitry, able to integrate gate drivers for SiC power devices. This development is based on the mature and stable Tungsten–Schottky interface technology used for the fabrication of stable SiC Schottky diodes for the European Space Agency Mission BepiColombo.

67 citations

Journal ArticleDOI
TL;DR: In this paper, a review examines potential CMOS monolithic and hybrid approaches in a variety of wide bandgap materials for power and RF electronics applications, which can switch large currents and voltages rapidly with low losses.
Abstract: Power and RF electronics applications have spurred massive investment into a range of wide and ultrawide bandgap semiconductor devices which can switch large currents and voltages rapidly with low losses. However, the end systems using these devices are often limited by the parasitics of integrating and driving these chips from the silicon complementary metal–oxide-semiconductor-based design (CMOS) circuitry necessary for complex control logic. For that reason, implementation of CMOS logic directly in the wide bandgap platform has become a way for each maturing material to compete. This review examines potential CMOS monolithic and hybrid approaches in a variety of wide bandgap materials.

53 citations