Roberto Rubino

Bio: Roberto Rubino is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Computer science & CMOS. The author has an hindex of 3, co-authored 8 publications receiving 36 citations. Previous affiliations of Roberto Rubino include Instituto Politécnico Nacional.

Re-Thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

Abstract: A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed.

Relaxation Digital-to-Analog Converter with Foreground Digital Self-Calibration

Abstract: A reference-free, fully digital foreground self-calibration strategy intended to automatically tune the clock frequency of Relaxation Digital to Analog Converters (ReDACs), as demanded for linear operation, is presented in this paper. The effectiveness of the proposed approach is demonstrated by computer simulations on a 10-bit, 2MS/s ReDAC designed in 40nm CMOS and operated from a 600mV power supply voltage. After the proposed calibration, the ReDAC is shown to operate near the optimal clock frequency achieving 0.98 LSB maximum INL, 1.00 LSB maximum DNL and 9.06 ENOB.

Relaxation digital-to-analogue converter

Abstract: The novel relaxation digital-to-analogue conversion technique, which takes advantage of the exponential impulse response of a first-order RC network to generate binary-weighted voltages, is proposed to design standard-cell based, mismatch-insensitive, ultra-low power, tiny digital-to-analogue converters targeting the requirements of Internet of Things applications. The effectiveness of the approach is validated by simulations and measurements performed on a proof-of-concept 10 bit, 300 S/s field programmable gate array prototype.

Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS

Abstract: A 10-bit-400kS/s and a 10-bit-2MS/s Relaxation Digital to Analog Converters (ReDAC) in 40nm are presented in this paper. The two ReDACs operate from a 600mV power supply, occupy a silicon area of less than 1,000µm2. The first/second DAC achieve a maximum INL of 0.33/0.72 LSB and a maximum DNL of 0.2/1.27 LSB and 9.9/9.4 ENOB based on post-layout simulations. The average energy per conversion is less than 1.1/0.73pJ, corresponding to a FOM of 1.1/1.08 fJ/(conv. step), which make them well suited to Internet of Things (IoT) applications.

Design Of Analog Cmos Integrated Circuits

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Re-Thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

Abstract: A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed.

Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation

Abstract: In this paper, fully-synthesizable Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) suitable for low-cost integrated systems are proposed both for voltage and current input. The proposed ADCs are digital in nature and are based on the Dyadic Digital Pulse Modulation (DDPM) Digital-to-Analog (DAC), instead of a traditional capacitive DAC. The proposed fully-digital ADC architectures enable low-effort design, silicon area reduction, and voltage scaling down to the near-threshold region. Compared to traditional analog-intensive designs, their digital nature allows easy technology and design porting, digital-like area shrinking across CMOS technology generations, and also drastically reduced system integration effort through immersed-in-logic ADC design. The voltage-input ADC architecture is demonstrated with a 40-nm testchip showing 3,000-μm 2 area, 6.4-bit ENOB, 2.8kS/s sampling rate, 40.4dB SNDR, 49.7dB SFDR, and 3.1μW power at 1V. A current-input ADC is also demonstrated for direct current readout without requiring a trans-resistance stage. 40-nm testchip measurements show a 5-nA to 1-μA input range, 4,970μm 2 area, 6.7-bit ENOB and 2.2-kS/s sample rate, at 0.94-μW power. Compared to the state of the art, the proposed ADC architecture exhibits the highest level of design automation (standard cell), lowest area, and the unique ability to cover direct acquisition of both voltage and current inputs, suppressing the need for transresistance amplifier in current readout.

BATMAN store-and-forward: The best of the two worlds

Abstract: The need for communication is highest in disaster scenarios when the infrastructure is also adversely affected. A recent protocol for ad hoc communication, the BATMAN protocol, is dependent on minimal infrastructure, in the form of mesh nodes that are used as access points, or nodes acting as an intermediary in a multi-hop connection. While BATMAN works well in a scenario in which there is a multihop path from senders to receivers at all times, it will drop the packets in intermittently-connected networks. Moreover, although implementation on a device is essential as a proof of concept, performing large scale evaluations requires a simulation platform in which variations in the operating environment can be studied. This paper is about adding the store-and-forward mechanism to the routing component in BATMAN nodes, to overcome intermittent connectivity through mobility. We describe an extension of the protocol, SF-BATMAN, that has been implemented in an interoperable manner with BATMAN, i.e. with no added signaling, and no change of basic BATMAN settings. We have implemented SF-BATMAN in a packet level simulator (NS3), and demonstrated its performance in a scenario that consists of two regions of connectivity: a well-connected mesh network and a set of sparser subnetworks. We show that the added capability enhances the performance of BATMAN, through an increase of the delivery ratio by 20% with a lower overhead, while it exhibits a similar latency in comparable network scenarios.