In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

In this paper we study the operation and working of a Dual Dynamic node hybrid flip-flop (DDFF-ELM) with an embedded logic module. It is one of the most efficient D-Flip-flops in terms of power and delay as compared to other dynamic flip flops. A double exponential current pulse is passed to the sensitive nodes of the circuit to model a radiation particle strike in the circuit. The faulty output is then corrected using a radiation hardening by design technique. All the circuits are implemented using Cadence 90 nm technology and a comparison is made between the power and delay of already implemented D- flip-flops.

Rohan S. Adapur

Papers

A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module