Romain Duru

Bio: Romain Duru is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Silicon & Metrology. The author has an hindex of 5, co-authored 24 publications receiving 76 citations.

Hydrogen passivation of silicon/silicon oxide interface by atomic layer deposited hafnium oxide and impact of silicon oxide underlayer

Abstract: HfO2 synthesized by atomic layer deposition (ALD) can be used as a passivation material for photodetectors. This paper shows a significant reduction of density of interface traps at the Si/SiO2 interface using ALD HfO2. This is explained by a chemical passivation effect due to presence of hydrogen from water used in the ALD process. Furthermore, ALD HfO2 layers appear negatively charged which generate an additional field effect passivation. The impact of the SiO2 underlayer is also discussed by comparing a chemical silicon oxide to a standard thermal silicon oxide. It is shown that chemical silicon oxide can act as a reservoir of hydrogen atoms which helps to reduce the density of defects close to the Si/SiO2 interface. This result demonstrates the importance of the surface preparation before the ALD of HfO2 in the passivation scheme. Finally, this work shows the correlation between negatively charged defects and Si–O–Hf bonds at the SiO2/HfO2 interface. A passivation stack composed of chemical oxide perm...

Photoluminescence Imaging for Buried Defects Detection in Silicon: Assessment and Use-Cases

Abstract: In this paper, the innovative photoluminescence imaging technique is described for applications to buried defect detection in silicon devices. The validity of this emerging technique is first assessed in comparison with well-established characterization techniques (defect selective etching of silicon, X-Ray diffraction topography, cross-sectional transmission electron microscopy imaging and photoluminescence spectroscopy). This paper then describes specific applications illustrating the use of the photoluminescence imaging technique for common processes of the CMOS semiconductor industry. The benefit of this fast, high resolution and non-destructive technique is demonstrated: this includes industrial use of the technique for in-line production control on product wafers.

Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

Abstract: For the first time, the interest of a new SiCO low-k spacer material deposited at 400°C is evaluated in the perspective of a 3D VLSI integration. The benefits of SiCO low-k (4.5 vs 7 for SiN) value is preserved throughout the whole integration and translates into a 5% decrease for both effective capacitance and delay of FO3 Ring Oscillators in a 14FDSOI technology. In addition, a NMOS breakdown voltage improvement of 3.5V and a decrease in leakage current of 0.7 decade is demonstrated on thick oxide devices. This electrical performance together with the low temperature deposition makes SiCO a very appealing candidate for 3D VLSI in a CoolCube™ integration scheme.

Oxidation kinetics of Si and SiGe by dry rapid thermal oxidation, in-situ steam generation oxidation and dry furnace oxidation

Abstract: The fabrication of ultrathin compressively strained SiGe-On-Insulator layers by the condensation technique is likely a key milestone towards low-power and high performances FD-SOI logic devices. However, the SiGe condensation technique still requires challenges to be solved for an optimized use in an industrial environment. SiGe oxidation kinetics, upon which the condensation technique is founded, has still not reached a consensus in spite of various studies which gave insights into the matter. This paper aims to bridge the gaps between these studies by covering various oxidation processes relevant to today's technological needs with a new and quantitative analysis methodology. We thus address oxidation kinetics of SiGe with three Ge concentrations (0%, 10%, and 30%) by means of dry rapid thermal oxidation, in-situ steam generation oxidation, and dry furnace oxidation. Oxide thicknesses in the 50 A to 150 A range grown with oxidation temperatures between 850 and 1100 °C were targeted. The present work shows first that for all investigated processes, oxidation follows a parabolic regime even for thin oxides, which indicates a diffusion-limited oxidation regime. We also observe that, for all investigated processes, the SiGe oxidation rate is systematically higher than that of Si. The amplitude of the variation of oxidation kinetics of SiGe with respect to Si is found to be strongly dependent on the process type. Second, a new quantitative analysis methodology of oxidation kinetics is introduced. This methodology allows us to highlight the dependence of oxidation kinetics on the Ge concentration at the oxidation interface, which is modulated by the pile-up mechanism. Our results show that the oxidation rate increases with the Ge concentration at the oxidation interface.

Photoluminescence for in-line buried defects detection in silicon devices

Abstract: In this work, a novel imaging photoluminescence-based metrology method is introduced, with potential application to buried defect detection in silicon devices during semiconductor manufacturing process. The theoretical and practical aspects are both discussed. A new metrology tool was realized and thoroughly tested through real-life semiconductor samples to reveal the capabilities of the suggested method. According to the results, defects down to the sub-micron size range can be optically detected, as confirmed by cross-sectional transmission electron microscopy images.

X-Ray Diffraction

Abstract: Interpretation of X-ray Powder Diffraction Patterns . By H. Lipson and H. Steeple. Pp. viii + 335 + 3 plates. (Mac-millan: London; St Martins Press: New York, May 1970.) £4.

Boosted UV Photodetection Performance in Chemically Etched Amorphous Ga2O3 Thin‐Film Transistors

Abstract: DOI: 10.1002/adom.201901833 the further promotion of devices’ performance.[7] As is well known to all, PPC phenomenon occurs in most oxide semiconductor materials owing to the large quantity of oxygen vacancy (Vo) defects and high density of trap states.[8,9] Phototransistors, one kind of three-terminal PD with one more terminal-gate to flexibly control the channel carriers’ transportation behavior, have been regarded as an alternative solution to improve the PD performance.[10,11] Phototransistor possesses the intrinsic gain of transistors and regular photoconductors, which makes it possible to achieve both high light-todark current ratio and responsivity.[11,12] Last but not the least, the PPC phenomenon is possibly eliminated by exerting a gate pulse, as Jeon et al. demonstrated in the three-terminal photosensor array with GIZO/IZO/GIZO channel.[5] For a-Ga2O3 UV PD or imaging applications, a research on fabrication and utilization of phototransistor architecture is urgently needed to well suppress PPC and raise the response speed while retaining a high photoresponsivity as well. Meanwhile, the controllable and selective etching of a-Ga2O3 channel to metals and other oxides is critical to the achievement of a low gate leakage current and good transfer characteristics.[13,14] Wet chemical etching of β-Ga2O3 has been demonstrated by using H3PO4 and H2SO4, respectively.[15,16] However, these strong acids will corrode metals and oxides readily, which bring a big trouble to device fabrication. In this paper, we present bottom-gate a-Ga2O3 thin film transistors (TFTs) and phototransistors where the a-Ga2O3 channels are selectively etched using tetramethyl ammonium hydroxide (TMAH) aqueous solution. Note that this new etching method owns the advantages of low cost, simple operation, good safety, and desirable compatibility with lithography. For the common bottom-gate Ga2O3 TFT on Si, the device with patterned channel exhibits superior transistor characteristics to the unpatterned one. A bottom-gate a-Ga2O3 phototransistor with interdigital finger-shaped source/drain (S/D) electrodes is prepared on quartz and applied to detect deep UV rays. It demonstrates typical transistor output and transfer characteristics with a high on/off ratio of ≈107. Meanwhile, an excellent photodetector performance appears under a 254 nm UV illumination, including a high lightto-dark ratio of 5 × 107 and responsivity of 5.67 × 103 A W−1. By applying a positive gate pulse, PPC in the a-Ga2O3 phototransistors is effectively eliminated with a fast decay in 5 ms. A three-terminal thin-film transistor (TFT) architecture is essential for photodetectors to reach a good balance between high responsivity and fast response speed. Bottom-gate amorphous Ga2O3 (a-Ga2O3) TFTs are fabricated to boost their UV photodetection properties. During the device fabrication process, a simple chemical-etching solution with the advantages of easy operation, low cost, and compatibility with traditional lithography process, is developed to selectively etch a-Ga2O3 films. The a-Ga2O3 channel etched device on Si manifests an effective suppression of the commonly observed gate leakage current. Meanwhile, a patterned a-Ga2O3 TFT on quartz shows an excellent n-type TFT performance with an on/off ratio as high as ≈107. It is further applied as a phototransistor, to diminish the persistent photoconductivity (PPC) effect while keeping a high responsivity (R) as well. Under the 254 nm UV illumination, the a-Ga2O3 phototransistor demonstrates a high light-to-dark ratio of 5 × 107, a high responsivity of 5.67 × 103 A W−1, and a high detectivity of 1.87 × 1015 Jones. Remarkably, the PPC phenomenon in a-Ga2O3 UV phototransistors is effectively suppressed by applying a positive gate pulse, which greatly shortens the decay time to 5 ms and offers a-Ga2O3 possible inroads into imaging applications.

SiGe BiCMOS Current Status and Future Trends in Europe

Abstract: This paper reviews the advantages of SiGe BiCMOS technologies and their applications in the millimeterwave to terahertz domains. The state-of-the-art covering both the Si/SiGe HBTs and the CMOS nodes is shown. Future perspectives and related main challenges are discussed with a focus on the ongoing European research activities through the presentation of the TARANTO project, whose main objective is to help developing 600 GHz $\pmb{f}_{\mathbf{MAX}}$ nanoscale SiGe BiCMOS platforms.

Deviations from Vegard's law in semiconductor thin films measured with X-ray diffraction and Rutherford backscattering: The Ge1-ySny and Ge1-xSix cases

Abstract: The compositional dependence of the lattice parameter in Ge1-ySny alloys has been determined from combined X-ray diffraction and Rutherford Backscattering (RBS) measurements of a large set of epitaxial films with compositions in the 0 < y < 0.14 range. In view of contradictory prior results, a critical analysis of this method has been carried out, with emphasis on nonlinear elasticity corrections and systematic errors in popular RBS simulation codes. The approach followed is validated by showing that measurements of Ge1-xSix films yield a bowing parameter θGeSi =−0.0253(30) A, in excellent agreement with the classic work by Dismukes. When the same methodology is applied to Ge1-ySny alloy films, it is found that the bowing parameter θGeSn is zero within experimental error, so that the system follows Vegard's law. This is in qualitative agreement with ab initio theory, but the value of the experimental bowing parameter is significantly smaller than the theoretical prediction. Possible reasons for this discr...