Rongsheng Yang

Bio: Rongsheng Yang is an academic researcher from Micron Technology. The author has contributed to research in topic(s): Shallow trench isolation & Short-channel effect. The author has an hindex of 2, co-authored 2 publication(s) receiving 5 citation(s).

Derivation of threshold voltage and drain current for cylindrical MOSFET and application to a recessed MOSFET

Abstract: Threshold voltage and drive current for a cylindrical MOSFET have been rigorously derived for the first time. An approximate expression for these quantities is presented for the purpose of analytical calculations. The model has been verified against TCAD simulations. The characteristics of a recessed gate MOSFET is analysed using these models.

Three-Dimensional Characterization and Modeling of Stress Distribution in High-Density DRAM Memory Cells

Abstract: The retention time characteristics in DRAM cells are strongly influenced by various leakage mechanisms near the storage node junction. In this work, we present a full three-dimensional analysis of stress distributions in and around the active area of high-density memory cells. We use a combination of high-resolution metrology analysis and 3D numerical modeling to provide quantitative estimates. Since shallow - trench isolation (STI) process used in high-density cells is one of the major contributors to stress, we study the effects of various materials used to fill the trench. Our electron diffraction contrast (EDC) methodology provides a spatial resolution on the order of 10 nm with sensitivity on of the order of tens of MPa and therefore useful for the analysis of scaled high density memory cells.

Accurate Modeling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical Performance

Abstract: A new approach is presented aimed at modeling mechanical stress effects which impact MOSFET electrical behavior. It is successful in accounting for mobility variations experimentally evidenced on complex MOSFET geometries. The newly developed mobility model proves to be an efficient way to include mechanical stress effects into standard simulation models. We show that stress effects can and should be taken into account in the IC design phase in present and sub 90 nm nodes CMOS generations.

Modeling of Polysilicon Depletion Effect in Recessed-Channel MOSFETs

Abstract: The polysilicon depletion effect is one of the key factors that degrade MOSFETs' performance. In this letter, a polysilicon depletion model for recessed-channel (RC) MOSFETs is presented. The model shows good agreement with numerical device simulation results. We also compare the polysilicon depletion effect of RC MOSFETs to that of planar MOSFETs.

Trends in memory technology - reliability perspectives, challenges and opportunities

Abstract: As DRAM and NAND cells are rapidly scaled deep into the nanoscale regime, meeting design and reliability requirements require deeper understanding of single-cell characteristics. Some of the challenges are common between these technologies while some are unique. New materials and cell structures are being introduced to address some of these issues and provide further scaling opportunities.

Modeling and Simulation of InAs Nanowire Transistors

Abstract: In this work, we have investigated the electron transport, frequency response and optoelectronic properties of state-of-the-art single InAs nanowire field effect transistors, using both a full-band Monte Carlo simulator and an advanced hydrodynamic simulator. We perform a detailed high-frequency analysis, calibrating our simulations with experimental measurements that are successfully reproduced. We are thus able to make predictions about the HF performance and via a small signal analysis we determine the intrinsic cut-off frequency and maximum frequency of oscillation.

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

Abstract: In this paper, we present 3-D-DATE, a circuit-level dynamic random access memory (DRAM) area, timing, and energy model that models both the front and back end of 3-D integrated DRAM designs from 90–16 nm, across a broader range of emerging transistor devices and through-silicon vias. This paper improves upon previous studies by providing detailed process models all the way down to the 16-nm technology node and incorporating DRAMs implemented with emerging gate transistor devices. Finally, we validate the model against both several commodity planar and 3-D DRAMs, from 80- to 30-nm process nodes, with the following metrics: energy with a mean error of 5%–1% and a standard deviation up to 9.8%, speed with a mean error of 13%–27%, and a standard deviation up to 24% and area within 3%–1% and a standard a standard deviation up to 4.2%.